Cadence Stratus High-Level Synthesis version 20.10.100 - 22.02.001 | 90.4 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled Stratus High-Level Synthesis (HLS) versions 20.10.100 - 22.02.001 is the first high-level synthesis platform for use across your entire SoC design.What's new in Stratus High-Level Synthesis (HLS) versions 20.10.100 - 22.02.001 What's new in releases========
Overview
========
The 20.10 p100 release of Cadence Stratus High-Level Synthesis
is the base release for the Stratus HLS 20.1 release stream.
The 20.1 release is a major feature release with many
improvements covering many aspects of the high-level
synthesis flow.
==========================
What's New in This Release
==========================
The highlights of this release are:
New Tcl commands
* New Tcl commands allow custom scripts to be used when the Stratus
automation environment launches tools such as Genus and Joules.
* New Tcl commands allow the user to control partitioning via scheduled
regions and datapath optimization (DpOpt).
* New Tcl option allows additional post-elaboration commands to be
executed after the default post-elaboration commands.
Expanded C++/SystemC support
* IEEE 1666 SystemC sc_vector support simplifies the use of arrays of
signals, ports, and submodules via a syntax similar to std::array.
* New synthesizable fixed point functions support reciprocal and
reciprocal square root.
* Support for threads without reset improves quality of results for
processes that don't require reset logic.
Flow enhancements
* Multiple SystemVerilog/Verilog verification flow are now supported.
* Encrypted technology libraries (*.enc) are now supported.
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Overview
========
The 20.20 p100 release of Cadence Stratus High-Level Synthesis
is the base release for the Stratus HLS 20.2 release stream.
The 20.2 release is a major feature release with many
improvements covering many aspects of the high-level
synthesis flow.
==========================
What's New in This Release
==========================
The highlights of this release are:
More powerful and flexible synthesis
* Automatically synthesize to user-defined memory architectures
* Optimized synthesis of nested or sequential loops
* New IP: pipelined floating point divider
More flexible use model
* Verilog modules can be instantiated in the SystemC hierarchy
* New Tcl command to synthesize entire module hierarchies
* SystemC assertions can be synthesized to separate SystemVerilog module
========
Overview
========
The 21.1 p100 release of Cadence Stratus High-Level Synthesis
is the base release for the Stratus HLS 21.1 release stream.
The 21.1 release is a major feature release with many
improvements covering many aspects of the high-level
synthesis flow.
==========================
What's New in This Release
==========================
The highlights of this release are:
More powerful and flexible synthesis
* Significant improvements to loop coalescing to accept more natural coding
styles for loops to be pipelined
* Loop Fusion. The ability to fuse sibling loops automatically.
* Operand isolation (for low power) is now an option for both DPOPT and
SCHEDULED regions
* Automated module redundancy allows you to specify that an entire module is
to be duplicated and results compared to the original. Important for ISO
26262 and applications where circuit redundancy is critical.
* Mux timing estimates have been improved to be more consistent
More flexible use model
* IDE upgrade to Qt 5 results in improved performance and stability
* BDW now supports Verilog testbenches (and hence, UVM) rather than strictly
requiring that the testbench is written in C++
* Improved register naming persistence across ECO
* Wire and Mux names in generated RTL maintain a more meaningful relationship to
SystemC
* Scheduled regions have been improved to allow more flexible input
* TCL API has been extended to provide access to power analysis runs (Joules)
* New divider architectures for the iterative dividers included in
cynw_utilities.h.
* Support for Multi-Vt libraries when running Genus on post-Stratus RTL.
========
Overview
========
The 21.2 p100 release of Cadence Stratus High-Level Synthesis
is the base release for the Stratus HLS 21.2 release stream.
The 21.2 release is a major feature release with many
improvements covering many aspects of the high-level
synthesis flow.
==========================
What's New in This Release
==========================
The highlights of this release are:
Core high-level synthesis features
* Schedule optimization for leakage power: the use of the new synthesis control attribute sched_optim_slack=leakage will implement a schedule that better spreads the slack out among the clock cycles to reduce the number of fast (therefore high leakage) parts used.
* Changes to the output_style_starc behavior: the STARC recommendations S2.2.3.1 (Do not mix blocking and non-blocking assignments in combinational always construct) and S2.3.1.1 (Use non-blocking assignments in FF inferences) are now always enforced.
* Changes in sharing of hls_dpopt_region resources: resources created using hls_dpopt_region command or the HLS_DPOPT_REGION directive will not be shared unless the regions have the same names.
* Array minimum distance constraint: a new command constrain_array_min_distance and directive HLS_CONSTRAIN_ARRAY_MIN_DISTANCE have been added. These operate in a similar way to the constrain_array_max_distance command and give the user additional control of the scheduling of read and write accesses to dual port memories.
* Packing of structure elements onto a single port: a new directive HLS_PACK_PORT has been added that causes the elements of the named structure to be packed onto a single port rather than each structure element having a separate port.
Language extensions
* Expanded support for sc_vector: a number of limitations on the use of sc_vector have been removed.
* Passing std::array through signals and ports: a new cynw_std_lib_signal_support.h header file has been added. Including this file will enable std::arrays to be passed through SystemC sc_signals and sc_in and sc_out
* Support for std::sort: Stratus HLS now supports synthesis of std::sort for in-place sorting of arrays.
IDE features
* Logic synthesis timing view: in the analysis view for the logic_synthesis_config there is a "Timing" tab that shows the paths with the worst slack in logic synthesis. There are links to the same path in the HLS timing view if the same path exists there.
* Schedule failure report viewer: the schedule failure report is now available in the Reports tab of an hls_config and contains cross-links to other views.
* Critical path in CDFG and Pipeline view: a button with the label "CRIT" has been added in the upper right hand corner of these views. Selecting this button causes the view to highlight the critical path.
* Setting the directory for libraries: the new default_hls_lib_dir_path attribute allows the user to specify a target directory other than the project directory for the directories associated with memlibs and iflibs.
* Viewing contents of datapath resources: a "Source Verilog" button has been added to the hls_config analysis dashboard. This allows viewing of the Verilog description that was the input to Genus Inside for the datapath resource. This is useful for understanding the I/O ports and contents of the resource.
* Pipeline active indication for integration with external power controllers: the define_pipeline_active_signal command and HLS_DEFINE_PIPELINE_ACTIVE directive have been added to cause Stratus HLS to indicate the active or idle status of pipelines.
* Enhancement of the power_config comparison table: the power_config comparison table has been enhanced to include the logic synthesis area and slack for power_configs that use the gate level representation of the design for analysis.
Verification features
* Stability of gate_enable_* names from baseline config to eco config: these names will be the same whenever possible.
* Reduction of unreachable RTL code: many instances of unreachable lines in generated RTL have been prevented.
* Use different stimulus files with a sim_config: the define_sim_stimulus command has been added to allow different stimulus files to be used with a single sim_config without recompilation.
* Version updates for g++: The 4.8 version of g++ is no longer supported. Support for the 9.3 version of g++ has been added.
* Enhanced support for Bullseye C++ code coverage: the Bullseye C++ code coverage tool can now be used for simulations in Xcelium.
Integration features
* Improved Joules integration: Additional options have been added for advanced power analysis including the use of an .sdc file, a .spef file and the ability to use a different library for power analysis than that used for synthesis. The version of Joules included in the Stratus HLS package has been upgraded to Joules 20.11.
* Improved Genus integration: A number of improvements have been made to the bdw_rungenus and bdw_runsgenus scripts for improved reporting and better clock gating.
* Suffix support in bdw_export: A -suffix option has been added to the bdw_export utility with similar functionality to the -prefix option.
* Jasper Superlint integration: The choice "superlint" has been added to the -command option of the define_analysis_config command. This invokes Jasper Superlint for RTl linting.
* Xilinx Vivado logic synthesis upgrade: Vivado version 2020.1 has been qualified to work with Stratus HLS.
IP
* Three multiplier complex multiplication function: A new utility function has been added to the cynw_complex header file for implementing the complex multiplication using fewer multipliers at the cost of some performance.
* sin_norm and cos_norm for unsigned fixed point datatypes
* New utility functions have been added to the cynw_fixed_utilities.h file to support sc_ufixed.
Changes Stratus HLS version 21.2 that you should be aware of:
You must use a compatible version of Xcelium, where Xcelium is compiled with -D_GLIBCXX_USE_CXX11_ABI=1. If you are not using a compatible version of Xcelium, an error will be generated when Stratus HLS performs a compatibility check for this at simulation runtime.
========
Overview
========
The 22.01 p001 release of Cadence Stratus High-Level Synthesis
is the base release for the Stratus HLS 22.01 release stream.
The 22.01 release is a major feature release with many
improvements covering many aspects of the high-level
synthesis flow.
==========================
What's New in This Release
==========================
The highlights of this release are:
Verification & Advanced node support
* Integration of iSpatial for improved PPA estimation
* Integration of Cadence® IMC and JasperGold® UNR for
code coverage analysis
* Support for probing (preserving) SystemC variables in RTL
* Ability to suppress warnings based on specified source lines
Runtime & Optimizations
* Improved runtime for long mux characterization
* Addition of FlexChannels trait to always assign prevents
creation of unused registers when nb_get and nb_peek
have unasigned arguments
IP
* Line buffer enhancement to disable reads while memories
are filling
* Packaging the previously named cynw_cm_float
class as a header file.
* Enable user-specified scaling of cynw_fixed sin/cos
functions
IDE
* Support external browser for externally created HTML
* Annotate delay shown at every node for the Pipeline
Diagram
OTHER
* Change in version numbering scheme to allow more
incremental releases
* Arrays can be split into multiple memories based on
address bits or data slices
* auto_stall has been made more robust through the
detection of additional conditions that prevent stalling
* Elements of an array of C++ structures can be packed
into a single bit-vector, so that the array can be mapped to a single memory
========
Overview
========
The 22.02 p001 release of Cadence Stratus High-Level Synthesis
is the base release for the Stratus HLS 22.02 release stream.
The 22.02 release is a major feature release with many
improvements covering many aspects of the high-level
synthesis flow.
==========================
What's New in This Release
==========================
Miscellaneous
* Improved handling of pipeline stalls for pipelines with scheduled regions with initiation interval greater than 1.
* Automatic clean/rebuild of Memory and Interface libraries
* Support for Array transformations on external arrays allowing more flexible access by hls_modules
* Deprecate cynw_cm_float - the cynw_cm_float has been replaced by cynw_float
* Improved comparison and error flag generation for HLS_DUPLICATE_SUBMODULE
Verification
* Generate an RTL assertion when multiple drivers simultaneously write to the same object
* Support for a project.tcl mechanism in support of Xcelium -scfrontend and other simulation options
* Support for Bullseye SystemC code coverage via Xcelium -sc_covtool option
* Support for multiple arguments for a parent sim_config
* Enable code coverage for both SystemC and Verilog in a single sim_config
Power Optimization
* Support for thread-level clock gating
* Support for user defined input exceptions for operand isolation allowing specified inputs to be excluded from input isolation (gating)
With Cadenc Stratus High-Level Synthesis (HLS), engineering teams can quickly design and verify high-quality RTL implementations from abstract SystemC, C, or C++ models. The models can be easily created using the Stratus integrated design environment (IDE). Stratus synthesizable IP for SystemC provides simulation and synthesis models for common bus-based and point-to-point communication protocols as well as common mathematical operations and datatypes. With Stratus HLS, SystemC models can be retargeted to new technology platforms and reused more easily than traditional hand-coded RTL. The Stratus graphical user interface (GUI) and Tcl API also allow designers to quantitatively evaluate tradeoffs between the PPA from within the high-level synthesis environment.MATLAB-to-SystemC Workflow for Cadence Stratus HLSWatch a step-by-step demonstration of how to use HDL Coder with the Cadence Stratus HLS high-level synthesis tool to create highly optimized ASIC implementations of MATLAB code. The demo features a floating-point, least-mean squares (LMS) digital filter in MATLAB. The HDL Coder workflow is used to generate fixed-point MATLAB code, from which HDL Coder can generate synthesizable SystemC code along with a SystemC testbench using simulation. Then Stratus HLS is used to explore alternative ASIC implementations.Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.Product: Cadence Stratus High-Level SynthesisVersion: 20.10.100 - 22.02.001 *Supported Architectures: x86_64Website Home Page : www.cadence.comLanguages Supported: englishSystem Requirements: Linux **Size: 90.4 Gb * included:Base_STRATUS20.10.100_lnx86
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** System Requirements:
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