[行业软件]Cadence SPB Allegro and OrCAD 17.40.000-2022 HF039 crack  win/liunx [复制链接]

Cadence Design Systems, Inc., a leader in global electronic design innovation, is pleased to announce the availability of HotFix 039 for OrCAD and Allegro 17.40.000-2022 is a sleeker and more modern version of the OrCAD and Allegro release, with enhanced usability and a slew of new productivity- enhancing features.

Cadence OrCAD and Allegro: What’s New in 17.40.039-2022 - Date: 12-01-2023



Fixed CCRs: SPB 17.4 HF039

===================================================
CCRID Product ProductLevel2 Title
=======================================================
2756296 ALLEGRO_EDITOR 3D_CANVAS Ability to split bend across cutout
2796563 ALLEGRO_EDITOR 3D_CANVAS 3D Rendering of layers appears incorrect.
2820734 ALLEGRO_EDITOR ARTWORK Context-sensitive menu issue in Japanese environment of OrCAD PCB Editor in release 17.4-2019
2849582 ALLEGRO_EDITOR DATABASE Netlist import doesn't finish
2860356 ALLEGRO_EDITOR DATABASE Allegro PCB Editor stops responding when clines are stacked on the same layer
2854635 ALLEGRO_EDITOR MANUFACT Allegro crashes/hangs if text is added to Cross Section Table "Table Notes" section.
2805884 ALLEGRO_EDITOR MCAD_COLLAB Shape subclass changing after importing IDF file
2880362 ALLEGRO_EDITOR MCAD_COLLAB IDF Import on Flex design with zone using Multi cross-section swaps symbols shapes incorrectly
2810059 ALLEGRO_EDITOR SHAPE Thermal ties not as expected
2686549 ALLEGRO_EDITOR UI_GENERAL The board file locks up when trying to generate drill legend
2828454 ALLEGRO_EDITOR UI_GENERAL Replaying script recorded in 'Macro record mode' for adding room outline hangs PCB Editor
2865593 APD SHAPE Adding fillet to uVia doubles the uVia-to-shape SN spacing
2882751 APD SHAPE When running Update Shape, the dynamic shape is voided with incorrect clearance
2852602 CONCEPT_HDL AWR_TRANSLATO con2ul_cmd fails to translate symbol for a cell with use of -d option without reporting any errors
2831459 CONCEPT_HDL CORE space at the beginning of the sentence is deleted.
2850517 CONCEPT_HDL CORE Why is net PWR_CNT not in net group HV_GRP1 in the constraint manager. It has that net_group attribute on the net. It wa
2793171 CONCEPT_HDL OTHER Variant editor and marking components as variants and DNI causing DEHDL to crash
2762447 PCB_LIBRARIAN SYMBOL_EDITOR Cant change documentation grid in NSE
1375245 PSPICE MODELEDITOR Improve error message while saving file if backup directory is read only
2179166 PSPICE NETLISTER PSpice Netlist Error but nothing in Session Log for attached testcase
1188042 PSPICE SIMULATOR INTERNAL ERROR – Overflow Convert
2115571 PSPICE SIMULATOR Circuit simulation should give error when an invalid MATLAB function is defined
2191276 PSPICE SIMULATOR Inconsistent bias point results with Vpulse source.
2238626 PSPICE SIMULATOR Tolerance of BJT's param from model is not taken account in PSpice Advanced Analysis v17.4 Assign Tolerance
2243592 PSPICE SIMULATOR Long .param statement in .include file NOT included, with no warning or error.
2657100 PSPICE SIMULATOR PSpice Monte Carlo error "Illegal parameter value in input file"
2704970 PSPICE SIMULATOR Incorrect bias point when VOFF is defined in curly braces for AC analysis
2818321 PSPICE SIMULATOR TOLERANCE ASSIGNED IN THE PSPICE MODEL IS NOT TRANSFERRED TO ASSIGN TOLERANCE FORM
2843629 PSPICE SIMULATOR Temperature Sweep and Parametric Sweep analysis give different results for DC source and IC component
470277 PSPICE SIMULATOR Node limitation for poly devices
2852640 PULSE ADHOC Pulse server fails to start with migration error after upgrade to HotFix 037 of release 17.4-2019
2849546 PULSE NPR Warning (SPPSUN-509) displayed while trying to map part properties in New Part Request
2852357 PULSE PART_MANAGER Parts are missing for OrCAD Capture design when imported into System Capture
2801217 PULSE R2PLM-LIBSYNC Error while Configuring the New Part Request
2864857 PULSE USER_MANAGEME Members of Pulse 'Designer' group are unable to write or update unlocked schematic
2844953 SYSTEM_CAPTURE BOM Generate BOM issue in System Capture.
2881056 SYSTEM_CAPTURE BOM BOM HDL failed to launch on user's machine
2894186 SYSTEM_CAPTURE BOM Unable to generate BOM in .csv format
2829283 SYSTEM_CAPTURE CAPTURE_IMPOR Schematic audit rule 'Voltage on capacitor is not per pin polarity' not working for design migrated from OrCAD Capture
2797465 SYSTEM_CAPTURE CONSTRAINT_MA When creating Xnets for mutil-section symbol it show some incorrect assignment of nets under Xnets
2853295 SYSTEM_CAPTURE CONSTRAINT_MA Creating Xnets for multi-section parts includes incorrect member nets under Xnets.
2781868 SYSTEM_CAPTURE FIND_REPLACE Find and replace doesn't replace all net names, and creates mismatches between net names and physical names
2867920 SYSTEM_CAPTURE FIND_REPLACE Pasting a string from a CSV or XLSX file appends a space to the end of the pasted string
2861670 SYSTEM_CAPTURE GRID Electrical grid locked at the site can be changed at project by changing Documentation grid
2854328 SYSTEM_CAPTURE IMPORT_DEHDL_ blocks refdes/ text changed after conversion of DE-HDL design to System Capture.
2867334 SYSTEM_CAPTURE NAVLINKS TCL-Command navlinks -gen/-off does not change state of View > Navigation links
2834715 SYSTEM_CAPTURE NETGROUP Generate BOM:This error occurs when the entity/verilog.v file is not in sync with the physical part used in the design
2752341 SYSTEM_CAPTURE PACKAGER Refdes suffix going wrong in split hierarchical blocks hierarchy after migration to System Capture
2616146 SYSTEM_CAPTURE PRINT System Capture: TOC overlaps watermarks
2869144 SYSTEM_CAPTURE SHORTCUTS Syscap crashes at the time of launch with tcl file placed at site
2463249 SYSTEM_CAPTURE SMART_PDF Logos are getting filled with black in the PDF generated using the Smart PDF option
2492124 SYSTEM_CAPTURE SMART_PDF Smart PDF: Transparent background of images changes to black background
2566961 SYSTEM_CAPTURE SMART_PDF Smart PDF fills the symbol bodies in black in the PDF output
2783394 SYSTEM_CAPTURE SMART_PDF Vertical pin numbers print with smaller font than horizontal pin numbers
2804954 SYSTEM_CAPTURE SMART_PDF Rotating images in System Capture causes issues with Smart PDF
2821267 SYSTEM_CAPTURE SMART_PDF PDF pin names are smaller when vertically oriented.
2831686 SYSTEM_CAPTURE SMART_PDF Vertical fonts appear smaller than the horizontal fonts in Smart PDF.
2882901 SYSTEM_CAPTURE SMART_PDF PDF pin names are smaller when vertically oriented
2794654 SYSTEM_CAPTURE SPECIAL_SYMBO Variables attached to custom page borders render inconsistently
2845159 SYSTEM_CAPTURE TABLE_OF_CONT System Capture crashes during Find and Replace with TOC_AUTO_SAVE set to TRUE
2855864 SYSTEM_CAPTURE UNIFIED_SEARC Syscap does not allow to make column visible in Unified search window
2883802 SYSTEM_CAPTURE UNIFIED_SEARC Getting SPPSUN-5 error while adding property header to Unified search.
2875747 SYSTEM_CAPTURE WIRING Adding inport to wire gives error: This operation leads to invalid connectivity.
The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.2-2016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located here

About Allegro and OrCAD 17.2-2016. The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
- OrCAD Flex and Rigid-Flex Technologies
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.2-2016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stack-up by zone for flex and rigid-flex designs, Inter-layer checks for rigid-flex designs, Contour and arc-aware routing.
- New Cross-Section Editor
In the OrCAD PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay.
- New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.2-2016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.
- OrCAD PCB Designer 17.2-2016 Features
The OrCAD PCB Designer 17.2-2016 release also include new features or enhancements targeted towards improving PCB editors’ productivity and ease-of-use. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.
- OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
- Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.
- PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.

Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.2-2016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located here

Product: Cadence SPB Allegro and OrCAD
Version: 17.40
Supported Architectures: lnx86
Website Home Page : www.cadence.com
Languages Supported: english
System Requirements: Windows *
Size: 12.3 Gb


* included

Base_SPB17.20.000_wint
Hotfix_SPB17.20.080_wint
Hotfix_SPB17.20.083_wint


* System Requirements:

Cadence Allegro and OrCAD 17.2-2016 Hardware and Software Requirements:

Operating System:
Microsoft Windows 7 Professional, Enterprise, Ultimate or Home Premium (64-bit); Windows 8 (64-bit) (All Service Packs); Windows 10 (64-bit); Windows 2008 R2 Server; Windows 2012 Server (All Service Packs).
Note:Cadence Allegro and OrCAD (Including EDM) products do not support Windows 7 Starter and Home Basic. In addition, Windows Server support does not include support for Windows Remote Desktop. Windows RT and Tablets are not supported.
Minimum Hardware:
- Intel Pentium 4 or AMD Athlon XP 2000 with multi-core CPU
- Ram:8 GB RAM
- Virtual memory at least twice physical memory
- 50 GB free disk space
- 1,024 x 768 display resolution with true color (16-bit color)
- Broadband Internet connection for some service
- Ethernet card (for network communications and security hostID)
- Three-button Microsoft-compatible mouse
Recommended Hardware:
- Intel Core 2 Duo 2.66 GHz or AMD Athlon 64 X2 5200+
- Note: Faster processors are preferred.
- RAM:8 GB RAM
- Disk:500 GB free disk space
- Display:1,280 x 1024 display resolution with true color (at least 32bit color)
- GPU:A dedicated graphics card
- Display:Dual monitors
- Microsoft Internet Explorer 11.0 or later
win版

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liunx版

Orcad 绝对🐂啊

很好，很强大。

Cadence SPB Allegro and OrCAD 17.20.000-2016 HF055

Cadence SPB Allegro and OrCAD 17.20.000-2016 HF057

Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled a new of improvements to the Cadence SPB Allegro and OrCAD 17.20 families of products aimed at boosting performance and productivity through improvements features and big fixed issues.

Cadence SPB Allegro和OrCAD 17.20.000-2016 HF059

升级了

感谢楼主，支持一下。

Cadence SPB Allegro and OrCAD 17.20.000-2016 HF063