Mentor Graphics HyperLynx提供了一套完整的分析和验证软件，可满足PCB工程师在电路板设计细节各个领域的需求。HyperLynx使PCB工程师能够有效地分析，解决和查看关键情况，以防止重复发生的成本。借助HyperLynx，您可以获得更多的创新，更快的上市速度并降低成本。HyperLynx的最新版本通过强调易用性和团队生产力来解决当今高级系统设计日益复杂的问题。 HyperLynx是用于高速电子设计的完整分析工具系列，包括电气设计规则检查（DRC / ERC），信号完整性（SI），电源完整性（PI）和集成的2D / 2.5D / 3D电磁建模（3D EM） 。HyperLynx允许您使用高级仿真技术在设计周期的早期发现并纠正问题，以预测设计的行为方式。布线前设计仿真使您可以探索替代方案以做出明智的设计决策，而布线后验证则使您可以在将设计提交到制造之前执行详细的签核分析。使用HyperLynx优化设计的性能和可靠性，可以增加一次成功通过设计的机会。Mentor Graphics Corporation, a Siemens business, is pleased to announce the availability of HyperLynx VX.2.10. The latest release provides significant new capabilities for the design and verification of high-speed serial (SerDes) links, DDRx interfaces, and board-level Power Delivery Networks (PDNs). New Features Introduced in HyperLynx VX.2.10 HyperLynx SI - Signal IntegrityHyperLynx SI VX.2.10 provides significant new capabilities for the design and verification of both high-speed serial (SerDes) links and DDR4/5 interfaces, along with improvements for general-purpose Signal Integrity.HyperLynx PI - Power IntegrityHyperLynx PI VX.2.10 provides significant new capabilities for the design and verification of board-level Power Delivery Networks (PDNs), including board-level thermal co-simulation.HyperLynx Advanced Solvers (3D EM)HyperLynx Advanced Solvers VX.2.10 provides significant new capabilities for accurate 3D EM modeling of critical areas in high-speed systems designs.HyperLynx DRC - Electrical Rule ChecksHyperLynx DRC VX.2.10 provides significant new capabilities for rapid checking of high-speed designs, including the ability to accelerate runs by distributing the verification task across multiple processors. HyperLynx VX.2.10 Release Highlights - Date: September 2021 New HyperLynx Features by Product HyperLynx SI/PI/Thermal - Overview
This release contains improvements in SERDES analysis, DDRx analysis, and DC Drop analysis, as well as some notable usability improvements
SERDES
- Taking advantage of the SERDES Compliance Wizard infrastructure improvements that were made in VX.2.8, HyperLynx VX.2.10 includes the addition of explicit support for over 70 new SERDES protocols. Furthermore, a new feature has been added for customers to add new protocols themselves.
- Reporting has been improved for clarity and consistency.
- When using the Compliance Wizard directly on S-parameters, those S-parameters can now be swept for solution space exploration.
- Standalone compliance/metric analysis in the Touchstone Viewer has been removed. The independent IBIS-AMI Wizard has also been removed. These capabilities have been consolidated into the SERDES Wizards.
- Automatic IBIS-AMI parameter optimization has been added to the SERDES IBISAMI Batch Wizard.
DDRx
- Can now sweep ACC and CLK buffer models in LineSim.
- Addition of ACC Overshoot measurements (per JEDEC spec).
- Support for diamond and hexagonal eye masks for DDR5 timing model development
PI Analysis
- New resistance matrix output in DC Drop analysis generates a matrix of resistances between sources and loads for resistance based PDN analysis
- Plating thickness and current constraints for vias can now be specified on a perpadstack basis.
General Usability
- New spreadsheet-based multi-board connection wizard allows for easier and more efficient setup of multi-board projects, especially those with complicated connector mappings. Connection mappings can be imported and exported for easy re-use between designs.
- Individual nets may now be selected for analysis in LineSim. This provides a dramatic performance improvement for very large schematics, including for analysis types like DDRx and SERDES.
HyperLynx DRC - OverviewHyperLynx DRC adds some important new functionality and defect fixes. The sections below provide details on some of the new capabilities.
Distributed verification
- By distributing Jobs on multiple CPUs or multiple PCs, run time is reduced, especially for large-scale verifications
- Work is distributed to each session on a rule-by-rule basis. The results are automatically aggregated into the hosting session.
- LSF can be used in an environment where LSF is set
- Setup is possible from Wizard
Database Compare
- A utility for Windows that uses External Automation. Detects the difference between the two designs.
- Example use cases are detecting differences in the design version or checkingwhether the reference design is completely copied to the target design.
New Rules
- Routing On/Off layer
- Trace shielding with stitching vias
- Via ani-pad integrity
Other major improvements
- DDR wizard is enhanced to be more robust.
- Many rules are enhanced to support more rule parameters for precise checking.
- Multiple custom rules can be complied in one step.
HyperLynx Advanced Solvers - OverviewThe sections below provide details of new capabilities in this version of the HyperLynx Advanced Solvers products.
New Capabilities
- New multi-stack modeler operations
. Fast editing of objects
. Edit bond wires, solder balls, lead frames
. Sweep parameters
. Dozens of new context menu operations
. Better Filtering, Select Similar, Locate, etc.
. Automatic snap to grid and grid rendering
. Show 3D model for meshing
- Full-wave Solver Huygens’ Box Import and Dipole Excitation
User Experience Improvement
- Fast edit mode for basic editing operations
- PDN Optimizer improvements / fixes.
- Improved launcher
- General Enhancements
. Technology dialog improvements (stack-up Areas tab, Table context menus & copying, etc.)
. Import designs (automatically add nets, etc.),
. Padstack/shape editing (<ALL/USED LAYERS>, Span, etc.)
. Mesh and Solver options dialogs
. EMI shape editing
. Crop dialog usability
. Sync layout extents, displayed objects, layout options, etc.
- UI for new model operations
. Convert short arcs to Lines, enforce pins aspect ratio, group traces
. Recover hatch information, arc information,
. Remove area fill (hatching), remove holes from shapes
- Show 3D model for Meshing
Import & Export Improvements
- Universal Allegro Translator (UAT)
- UAT available for ODB++ (Windows and Linux)
- Complex via (CVP) import
Integration and Scripting Improvements
- Rigid Flex Flow improvements
HyperLynx 3D Explorer Improvements
- New template: Microstrip with Dk Control
- Sweep via padstack, start/end Layers
- Extend drill above/below support
- {{AUTO}} keyword for layer names
- Improved UI/UX: Recent templates, better layout, improved first-time experience
- Expert mode
- Better help (tooltips and HTML),
- Web browser enhancements (Back, Forward, Find, Zoom, Launch), etc.
Distributed Execution Improvements
- Job Distribution HyperLynx DRC rule verification support
- Job Distribution App support/simulate in cluster
- Distributed solve "Solve via PSH"
- PBS/Slurm/NC command line support
Accuracy and Solver Improvements
- Analysis of finite dielectric inclusions in layered medium
- Solver engine improvements can lead to 30-40% performance improvement
- New Excitations:
. Huygens Box excitations
. Dipole excitations
. Improved plane waves table
HyperLynx以其易用性而享誉业界，其自动化的工作流程使刚接触电源和信号完整性的设计人员可以进行复杂的分析。HyperLynx与Mentor的Xpedition和PADS Professional流程紧密集成，还可以与所有主要的PCB布局系统一起使用。 Mentor Graphics HyperLynx软件的功能： - 快速的信号完整性（SI）生产，在PCB设计系统中轻松，准确地进行信号完整性分析
- HyperLynx SI帮助工程师管理规则，规则的定义和有效性。
- 通过最终设计批准的无缝原理图设计，可以准确解决典型的高速设计效果。
- 确定可能会干扰电路板设计逻辑的潜在电源集成问题，并评估解决方案。
- 使用HyperLynx®DRC对EMI / EMC问题，信号完整性和电源完整性进行PCB设计审查。
- 通过对象自动化模型（AOM）访问数据库对象，并允许对这些对象进行高级几何操作。
- 提供对设计数据库的唯一访问
- 支持VBScript和JavaScript，标准AOM和DRC编程的完整文档
- 在不简化结构的情况下创建精确的EM仿真，确保结构精确
- 提供可扩展的模拟电路仿真
新功能介绍优化PDN去耦HyperLynx解耦优化器使您可以提高设计的配电网络（PDN）的性能，同时减少组件数量和成本。它使用几种不同的策略基于阻抗目标分析您的设计，使您可以选择最能满足您独特设计需求的解决方案。
增强型功耗意识分析增强型功耗意识分析配电网络（PDN）与高速信号交互，从而减少了设计余量。使用HyperLynx进行的Power-Aware仿真可精确模拟驱动设备I / O电源轨上的电压压缩（SSN）和高速信号的行为，包括其返回路径（而不是像大多数SI工具一样理想化返回路径行为）。现在，您的设计用于功率感知分析的自动3D EM提取比以往任何时候都更加自动化和轻松！
路由后3D EM自动提取路由后3D EM自动提取PCB设计的高精度布线后仿真是一种平衡行为。使用3D EM求解器对整个网络进行建模需要大量的内存和计算能力，即使使用标准方法可以准确而有效地实现大多数网络。诀窍是仅使用3D EM对不连续性进行建模，并将这些模型与标准模型正确集成，以进行其他所有操作。HyperLynx路由后3D EM自动识别需要3D EM分析的区域，对其进行求解并创建具有整个网络的模型，从而准确说明3D EM模型中包含的任何跟踪段。没有更简单或更快速的方法来执行高精度的路由后分析！
优化与3D EM的互连优化与3D EM的互连HyperLynx 3D Explorer使您可以通过3D EM仿真来扫描设计几何形状和模型行为，以创建满足设计电气性能需求的结构。通过转换，组件扇出，阻塞电容器布局等进行优化。3D Explorer使您可以从预配置的模板库开始，或从PCB布局创建自己的项目。
模拟PCB寄生效应以进行模拟/混合信号仿真模拟/混合信号仿真的PCB寄生建模PCB寄生效应可能是现代模拟/混合信号设计中的关键因素，但在设计仿真期间通常会忽略它们对电路性能的影响。这可能导致设计无法达到其性能目标，或者必须在制造后进行手动调整。Xpedition AMS与HyperLynx Advanced 3D EM求解器之间的集成使PCB寄生能够被精确建模，并在PCB出现问题之前被包括在AMS仿真中，从而可以快速而准确地进行设计调整，从而大大增加了首次通过设计成功的机会。
电气规则检查：刚性-柔性和引线键合电气规则检查：刚性-柔性和引线键合仅检查部分互连是否符合电气规则，很容易犯设计错误。HyperLynx DRC一直检查设计是否符合电气，物理和基于标准合规性的规则，一直到管芯焊盘。也可以在刚性挠性组件的整个长度上检查规则 试金石查看器增强功能S参数文件是准确建模频率相关行为的一种好方法，但是其基于数据的，基于频域的性质可能使您难以理解设计的实际行为–大多数系统设计人员自然不会想到频率域。HyperLynx Touchstone查看器可以自动识别和显示S参数网络中的通过路径行为。它还可以识别信号耦合高于用户指定阈值的所有端口对，从而易于发现问题区域以进行深入研究。系统要求Windows 7 / 8.1 / 10处理器：最低双核Intel或AMD处理器
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