Altair PollEx 2023 | 900.9 mb
The Altair development team is pleased to announce the availability of PollEx 2023 is a PCB-level Electronic Design Automation (EDA) software suite covering design review, analysis and manufacturing. Release Notes: PollEx 2023PollEx 2021.1 is available with a long list of new features, corrections, and improvements. If older version of PollEx installed on a machine, it should be deleted first and installed the PollEx 2021.1. This chapter covers the following: Highlights of the 2021.1 Release SALIENT FEATURES
Adding and modifying new license features
• New license feature code: PollExMFG is added for the PollEx manufacturing options which will draw the same 30 AUs.
• Changed license feature code: PollEx UPE application is available in PollExBasic feature which will draw 10 AUs from 30AUs.
Adding Altair License Utility
• Altair License Utility is added in PollEx 2021.1 launcher.
Adding Altair License Management System setup panel
• The environment variable setting panel is added during install. This panel is only displayed if the environment variable has not been set.
Adding design data saving option in PollEx PCB
• Added a feature to save design data in a project directory with a compressed file (*.tgz) to share relevant data conveniently.
Added SI Explorer
• Added a feature to support pre-layout analysis SI Explorer menu. A feature to perform pre-layout analysis was added. PollEx SI Explorer menu allows to validate the design decisions throughout the design process including the selection of parts, add materials, construct board layer stack-up and create the net topology.
• Upon executing PollEx SI Explorer, the SI Explorer dialog comes up. You can start pre-layout signal integrity analysis from the scratch.
. Create layer stackup
. Create VIA model
. Create Transmission Line Model
. Create Net topology (Single-ended, Differential, Multi-coupled)
• Perform Signal Integrity Analysis (Waveform, Eye-diagram, Network Parameter)
Adding a feature to display S/Y/Z parameters
• Adding a feature to display S / Y / Z parameter in Network Parameter viewer, PollEx SI. By using this function, it is possible to compare and measure by opening the S / Y / Z parameters extracted from various conditions
Adding an automation feature to support Multi-PCB structure
• Added a feature to generate system-level net topology automatically. By using this function, multi-level topology configuration and analysis between PCBs with different stackup is possible.
• Note: In version V2021.1, only single net (Single-ended, Differential Pair) analysis is possible. The analyze function of multiple net topologies will be released in V2021.2 version.
Adding a feature to support Rigid/Flexible PCB design
• System level signal integrity analysis is possible considering the multiple stackup structure of a design designed as a Rigid/Flexible structure
Adding a feature to extract SPICE Netlist
• Adding a feature to extract SPICE Netlist, you can select and determine the results of network parameter analysis. You can specify the output of the network analysis. (S/Y/Z Parameter, Spice Netlist, PSPICE Netlist)
. S/Y/Z Parameter: Network Analysis results are displayed as S/Y/Z parameters.
. Spice Netlist: Network Analysis results are saved in Berkeley Spice compatible format. (*.sp)
. PSPICE Netlist: Network Analysis results are saved in PSPICE compatible format. (*.lib)
Adding a feature to assign analog input
• Added a function to apply analog waveforms such as sinewave as an analysis stimulus during network analysis
PollEx 2021.1 Release Notes The most notable extensions and improvements to PollEx are listed by component
Feature
• Added a feature to save design data in a project directory with a compressed file (*.tgz).
• Added a feature for paring a differential pair net using a net string.
• Added a Pad Measure Base option in the Hole Through Pad item that set overlapped area of a pad and a solder mask (Pad+Solder Mask Overlap).
• Added a Checking Type option in the Copper Connected Pad item that you can select a type either Connected copper width ratio or Exposed copper area ratio.
• Added an option in the Net Group Shield item to pass if any one of the top or bottom side meets the checking criteria during the vertical shield check.
• Added a VIA Shielding option in the Diff – Complete Shield item.
• Added a feature to automatically set Component/Net Groups using the Part Classification set in UPE.
• Added a Net’s Input Setting menu in the Input dialog to check a grouping information of components or nets.
• Added an option in the IR Drop to check Allowable IR-Drop Value registered in the UPE.
• Added an option in the PDB Impedance to check using Target Impedance Value registered in the UPE.
• Added an option in the Result Table Export menu to export Result Area Image and ECAD Link Info.
• Added the TDR analysis type in the Network Analysis. With this option, the impedance waveform seen from the driver stage of the entire net structure can be analyzed. In this version, multiple reflections are not considered, and will be considered in our next release.
• Added a feature to select and determine the results of network parameter analysis in the Network Analysis. You can use this constraint to specify the output of the network analysis.
- S/Y/Z Parameter: Network Analysis results are displayed as S/Y/Z parameters.
- Spice Netlist: Network Analysis results are saved in Berkeley Spice compatible format. (*.sp).
- PSPICE Netlist: Network Analysis results are saved in PSPICE compatible format. (*.lib).
• Added a feature to apply analog waveforms in the Network Analysis such as sinewave as an analysis stimulus.
• Added a feature to support the Rigid/Flexible PCB design. By using this function, system level signal integrity analysis is possible considering the multiple stackup structure of a design designed as a Rigid/Flexible structure.
• Added a Network Parameter Viewer to display S/Y/Z parameters. It is enabled to compare and measure by opening the S/Y/Z parameters extracted from various conditions.
• Added an option to specify the Drill Layer when importing a design data.
• Added a command line to convert design unit.
• Added a command line to create a UPF file (/EXPORT_UPFS).
• Added an option to specify the Silk Layers for Top and Bottom when importing a design data.
Resolved Issues
• Modified to display Vdiff waveform of Differential Pair Net in the Waveform Viewer when analyzing Eye-diagram in the Network Analyzer.
• Modified to change the value of the passive component in the Net Topology Analyzer.
• Enhanced to use both Period(ps) and Frequency(MHz) when setting the operating speed of the signal in the Network Analysis.
• Enhanced a feature to generate system-level net topology automatically. Multi-level topology configurations and analysis between PCBs with different stack-ups are enabled.
• Modified the PDN Analysis to analyze even when polygons are directly connected to pins.
• Added a feature to analyze not only the heat of the active component, but also the effect of the heat of the trace joule.
• Added a feature to support Rigid/Flexible PCB. By using this function, thermal analysis is possible considering the multiple stackup structure of a design designed as a Rigid/Flexible structure.
• Fixed a bug that the partition name was not applied when adding a logic symbol using a functional symbol.
• Fixed a bug of incorrect dimensions of SOD123 package in the Generate Package Wizard.
SALIENT FEATURES
Adding a feature to export layer images
- PollEx PCB supports to export images of Artwork layers and Physical layers. Supported formats are *.JPG and *.BMP formats. The feature can be used from the menu File – Export To – Image in PollEx PCB.
Adding a feature to support LPDDR4 analysis
- A function to analyze LPDDR4 added to the Automatic DDR Bus Analysis feature in PollEx SI. LPDDR4 timing standard table was added.
In the existing DDR technology, the Vref voltage, which is the measurement reference for timing data and address buses, was used as a fixed value, but the Vref voltage in LPDDR4 is generated inside the IC through the training process. If the Extract Vref_DQ using analysis result option is used, the Vref value is searched in the manner specified by JEDEC. As a result of analysis for all data/address buses of ICs, the voltage level at which the eye is the widest open is obtained, and the Vref value is determined by their middle values. If the Use user defined value option is used, user can set the required Vref value.
Replacing SI to HyperSpice Engine
- The Spice engine of PollEx SI has been changed to HyperSPICE from Polliwog Spice since only the Spice engine was changed internally with same user GUI. However, the default Spice Control Parameter is changed.
Adding a feature of impedance map
- A function to display the Impedance Map in the result of the Impedance check item of PollEx DFE+ was added. After performing the Impedance check upon clicking the Impedance Map button in the result table, the Impedance Map dialog is displayed. By using this menu, user can easily find the impedance mismatch area in the full path of the entire BUS.
Adding a feature of crosstalk coupling table mapping
- A function to display the Backward Crosstalk Coefficient(kb) Coupling Map in the result of the Crosstalk Noise check item of PollEx DFE+ was added. After performing the Crosstalk Noise check upon clicking the Coupling Map button in the result table, the Coupling Map dialog is displayed. By using this menu, user can easily find the areas where crosstalk is vulnerable in the full path of the entire BUS.
Adding a Power Integrity Check feature
- A function to check Power Integrity has been added to PollEx DFE+. The newly added functions are IR-Drop, Loop Inductance, and PDN Impedance.
- IR-Drop Check
IR drop refers to a voltage drop that appears at the resistance component of power network. IR drop is the electrical potential difference between power source and load component during a current flow. If the voltage level supplied to the component is lowered due to IR-Drop, the system malfunctions or the Rising/Falling time of the signal is delayed, causing a Signal Integrity problem. Therefore, in order for the component to work properly, it is necessary to check whether the amount of IR-Drop is within the limit value allowed by the component. This item checks whether the voltage level of the specified component is lower than the specified level.
- Loop Inductance Check
In PCB, the power line generally refers to a power network that connects the power source(VRM) and the load components. The characteristics of these power trace configurations can be determined by the power delivery network (PDN) of the PCB. PDN operates like a passive component such as a coil or capacitor, depending on its physical properties. Resonance occurs due to these passive components, and the current flowing through the resonance structure causes signal distortion and EMI problems. PDN impedance should be designed as low as possible. Usually, in order to make the PDN impedance low, a decoupling capacitor is installed around the power pin. For this decoupling capacitor to work effectively, the loop inductance between the power pin and the decoupling capacitor must be designed to be small. This item checks whether the loop inductance between the power pin and the decoupling capacitor exceeds the value specified by the user.
- PDN Impedance Check
In PCB, the power line generally refers to a power network that connects the power source(VRM) and the load components. The characteristics of these power trace configurations can be determined by the power delivery network (PDN) of the PCB. PDN operates like a passive component such as a coil or capacitor, depending on its physical properties. Resonance occurs due to these passive components, and the current flowing through the resonance structure causes signal distortion and EMI problems. Therefore, precise analysis of PDN Impedance is very important in the design phase. This item checks whether the PDN impedance of the specified Power Pins are higher than the target impedance specified by the user.
Adding a feature to export thermal results
- In PollEx Thermal, a function to output the thermal analysis result in standard file format was added. Analysis results can be output in Excel format or .CSV format. At the Thermal Analysis Dialog, using File/Export to CSV menu, user can generate result file. Among the analysis results, the PCB Top/Bottom surface temperature is saved as designname_Top/Bottom.xlsx file, the saved format is the X,Y coordinates and temperature values, the component temperature is saved as the designname_Component.xlsx file, and the saved format is the Reference Name , PlaceLayer, X/Y coordinates, and temperature values.
PollEx is the most comprehensive and integrated set of PCB design viewing, analysis, and verification tools for electrical, electronics, and manufacturing engineers. PollEx transfers data flawlessly between the industry’s most popular ECAD and simulation tools and enables many of the world’s major electronics corporations to quickly visualize and review PCB designs. Its checking tools detect issues early in the design to avoid product failures and simplify manufacture and assembly. PollEx 2021 is available with a long list of new features, corrections, and improvements. Samsung SDI Improves PCB Development with Altair PollEx Altair is a global technology company that provides software and cloud solutions in the areas of product development, high performance computing (HPC) and data analytics. Altair enables organizations across broad industry segments to compete more effectively in a connected world while creating a more sustainable future. Product: Altair PollExVersion: 2023.0Supported Architectures: x64Website Home Page : www.altair.com
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