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AWR Design Environment Version 16 (V16) with groundbreaking cross-platform interoperability to support RF to millimeter wave (mmWave) intellectual property (RF IP) integration for heterogeneous technology development across the industry-leading Cadence Virtuoso design platform as well as the Allegro PCB and IC package design platforms. The V16 release also introduces seamless integration with the Clarity 3D Solver and Celsius Thermal Solver, delivering unconstrained capacity for electrothermal performance analysis of large-scale and complex RF systems. The new AWR Design Environment, including Microwave Office circuit design software, enables customers to efficiently design 5G wireless and connected systems forautomotive, radar systems, and semiconductor technologies and get to market faster. Platform and solver integration in the V16 release provides up to a 50% reduction in turnaround time (TAT) compared to competing workflows.

Platform interoperability is crucial to expediting RF integration and promoting engineering productivity. Seamlessly sharing design data among the AWR Design Environment, Virtuoso, and Allegro platforms eliminates any disconnect between RF design and manufacturing layout teams, saves valuable engineering resources and positively impacts development schedules. With the V16 release and its deep electromagnetic (EM) and thermal embedded analyses, customers are seeing more than a 3X reduction in TAT.
Key features in this release include:

Allegro integration: Ensures manufacturing compatibility and RF integration with PCB and IC package design flows
Virtuoso integration:Leverages Microwave Office for RF front-end design IP and combines it with the Virtuoso Layout Suite for IC and module integration
Clarity integration: Enables EM analysis for design verification of large RF structures such as module packaging and phased-array feed networks
Celsius integration: Provides thermal analysis for monolithic microwave IC (MMIC) and PCB high-power RF applications
AWR enhancements:Accelerates RF IP creation with advances in design automation and finite-element analysis (FEA) solver performance

AWR Design Environment V16 supports the Cadence Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence and system innovation. The V16 platform has been released and is now available for download. For more information, please visit www.cadence.com/go/AWRV16.