[行业软件]Cadence CONFORMAL 23.20.200 [复制链接]

Cadence Design Systems, Inc. has unveiled CONFORMAL 23.20.200 is the leading equivalence checker on the market and it does everything from RTL to GDSII.



Fixed CCRs for Conformal 23.2 Base p100

LEC:

2530182 huge runtime for abort analysis
2586115 add NEQ source_diagnosis to write_do_lec
2623593 LEC failure due to Innovus changing the function of primary pin after duplication
2636540 add tcl "set" commands to the LEC run script and the run_verify generated script
2643394 enhancement request to configure isolation assertion with run_verify
2686637 document filter_collection, compare_collections and collection
2693731 incorrect instance name got added
2746278 false NEQ
2762621 questions for using the official R1R2 NEQ list flow & document
2786744 document "-name_match" switch in "add_instance_equivalence" command
2787756 in case of conflict, map reachable flops together first
2800661 3 DFF NEQs related to cut points
2801719 enhancement request to report async set/reset feedback loop for a register
2810202 not able to functionally map/merge *_dop_* keypoints
2814147 R1R2 has 2 NEQs, but "guided ECO" compare has 91 NEQs
2815545 enhance testcase packager to update verilog filelist with correct design and include dir paths
2816165 initmap aborts
2817584 cannot restart checkpoint
2818914 right click to delete map point from compare point window
2818916 show diagnosis point type at front
2818927 cannot show modules from schematic to hier design browser
2819090 enhancement to allow user to gracefully remove conformal_project.cfm
2820614 need recipe for top module aborts for RTL to gate comparison
2824862 NEQs for the retimed module
2824878 "analyze_sequential_constant" internal error, but run continues
2826027 run is stuck during analyze and dynamic hier
2830320 crash during elaboration
2831137 abort module
2835395 "compare_recipes" draws excessive Smart LEC licenses than expected
2837208 does LEC support SLES15 version?
2840652 enhancement request for adding detail in "test_renaming_rule -test_module <mod*>" command
2840759 crash when restarting checkpoint
2841131 core dump when switched to auto_substitite
2841466 lsf compare_recipes hangs with go_hier
2844398 "add_pin_equivalence" error
2845199 8 NEQ in seq_constant golden only flow
2845696 question on System Verilog interface elaboration
2845859 question on workers in compare recipes parallelization
2848686 crash during elaboration
2850364 abort module
2851176 "get_unmap_points" crash
2851883 liberty parsing error
2851995 "analyze_abort -source -out" hangs starting 23.10-d230
2852438 error: total number of instances and gates 5345041612 exceeds limit during reading design
2852695 document new command "close project"
2853595 "restart_checkpoint" shows unknown rule name
2854640 NEQ in rtl v post_retime_syngen netlist
2854725 long runtime for gated-clock modeling
2854850 "compare_recipes RS8" crash
2857625 traceback triggered in compare_recipes.py
2857914 crash during "analyze_compare"
2858822 parser error when processing Verilog command file
2859819 "write_blackbox_wrapper" rename instance issue
2860205 abort module
2860298 "run_hier_compare" as a result of downgrading "go_hier_compare" errors out if non-common option is used
2860859 enhancement for "write_hier_compare_dofile -report_command" command to use in tclmode
2860967 "write_hier_compare_dofile" crash
2861756 elaboration error looks invalid, does not appear in Genus
2863515 load multiple parameters from same named library without overwriting
2864249 "go_hier_compare" passes but run_hier_compare" aborts
2864286 RS8 recipe crash
2870460 keypoint mapping cannot be done with renaming rule, but done with "field_delimiter"
2629795 1-pass run is hangs while using -function_pin_mapping attribute
2677673 HDL error
2725795 hang issue with 22.10-s200 version
2740511 enhancement to support more optimized designs- datapath/ungrouping/boundary opto
2743692 enhancement for "get_map_points" command to report unreachable keypoints
2790752 localparam name is getting appened to module name
2801413 checkpoint size reduction
2807142 false NEQ with partial assignment of record datatypes
2811198 enhancement request to compare fan-in cone (instead of comparing 0/1) on constant DFF
2827659 "read_design" memory increase with crash
2832604 hangs issue for "analyze_aborts" with 22.10+ versions
2840738 "read_implementation_information" reports debug information and exits when cyclic info is encountered
2842221 continuous dynamic flattening on on top module; run does not stop
2842946 crash during compare
2846015 compare_recipes usage of -kill_command_line
2850463 enhancement for "add renaming rule" command to control case sensitivity
2850750 "analyze_eco_recipes -patch_quality_formula" option does not work correctly when defined with space
2856471 enhancement to print the commands executed in the main logfile for compare recipes parallelization
2859071 does "add_notranslate_filepathnames" take wildcard on file paths?
2862913 LEC does not elaborate the ports correctly, local struc param is used instead of the passed down one
2863599 is there a way to report RTL loops with a command or in some RTL message?
2865623 wrong SV2.5b detected
2867771 document "UNCONNECTED%d$ UNCONNECTED_HIER_Z%d$?? on "set_mapping_method -Z_NAMEMAP_EXCLUDE"
2867883 tmr validation crash
2869946 aborts
2871180 "analyze_abort" resulted all EQ, but DP22 recipe resulted "Unmapped" in hier run
2872688 bbox compare shows all EQ, but there are not-mapped bbox input pins not checked
2872689 request to update document "add_mapped_point -skip_auto_pin_binding"
2873354 aborts
2873774 request to document command "report_feedback_registers"
2875811 aborts
2876427 aborts
2877828 request to change the wording in VLG6.2 message
2878991 LEC errors out when parsing non-compliant verilog1995
2881151 false RTL7.16 error from VHDL
2881154 crash during elaboration
2881304 document the new switch "-batch_command_return_pattern"
2881307 mismatched ports with "-BOUNDARY_MAPPING_FILE fv_map.user_hier.json" due to wrong RTL name
2881858 RTL fails to elaborate in 23.10s300 but elaborates successfully in previous version
2884725 presence of second entity using same generic map as first causes LEC elaboration issue
2884792 compare_recipes crash
2884895 crash when elaborating design with VHDL module instantiated in verilog module
2886487 abnormal exit during LEC run
2888839 VLG3.7 error
2889426 unable to parse a complex datatype declaration in a generate block
2889502 document man page for "set_hdl_options -SV_2STATE_DASSIGN_CHK" (RTL7.32f)
2889513 update Synthesis/Simulation Mismatch rules online doc and "report_rule_check -hdl_category -help"
2889520 add RTL rule 7.32f and 7.33 in "CAT_SYNSIM_mismatch" list
2890766 "analyze_design -unreach" hangs

ECO:

2293780 flatten ECO implementation flow (FEF)
2739913 request to add a module into the CECO CAT regression suite
2772865 error in "apply_patch"
2783845 ECO touching non ECO logic
2814876 request to reduce patch size without using user cut points on ICG
2823520 CECO adds unnecessary ECO nets into the netlist at dangling port
2832848 CECO unexpectedly changes data cone of some bit of a MBF which get split
2844386 method to obtain a list of new/ECO flop in the patch in a manual ECO flow
2846064 enhance "connect" from a net to a pin or port in a different hierarchy
2846641 simplified run crashes at adding ECO cut points
2848923 CECO crash in latest versions
2851110 update document to include G1G2 flow
2851447 error: detect inconsistent patch function at the same nets in "analyze_eco"
2854018 document options to globally set for "analyze_eco" & "compare_eco_hier"
2854870 CECO reports an internal error with the latest 23.10-d236 version
2857488 crash during guidance flow
2858413 "analyze_eco_recipes" error in vpxmode
2859470 CECO deletes and later adds 2 ICGs w/o connecting their TE pins
2860263 option "optimize_patch -sequentialnaming" doesn't work as expected
2862452 crash during "compare_eco_hierarchy" when we use "vpx set flatten model -enable_analyze_hier_compare -eco"
2863037 CECO doesn't recognize ECO rules with manual editing option enabled
2863051 CECO ignores option "report_eco_check .. -dofile" with manual editing option enabled
2869673 CECO missing add eco output pins related to test
2873139 CECO disconnects Q12 of an MBF and thus broke the scan chain
2609927 update the information in Pre-Mask ECO Flows chapter
2852713 broken scan chain due to a deleted scan flop
2858968 document "Patch size improvement with automatic cut insertion" has wrong figure in web_interface
2860179 enhance ECO recipe flow to include "optimize_patch" + "verification_info" for each strategy
2876005 ECO behavior changed on "eco_merge" starting 23.10-d323 version

CLP:

2167604 enhancement to highlight instance in schematics
2266894 find pin for simplified schematics with virtual power instances
2640766 enhancement to filter attributes during Liberty vs UPF compare
2655504 enhancement for CPX mapping method
2656148 enhancement to support model based port attributes with different module name in CPI
2690777 enhancement for traceback enhancement for "compare_liberty_upf"
2701920 issue with CPX connection of "create_power_switch ack_port"
2713395 enhancement to generate an executed command file from Verify
2743310 enhancement to enable recognition of buffered iso_enable signal
2772110 CPX failure from 2 ls cells added by one policy
2776465 enhancement to report "-replace" option for "read_power_intent" to issue an error
2799805 enhancement for adding "add_rule_filter" to included command sets for "run_verify"
2816902 incorrect driver/recvier supply on ports in top/partiton
2827366 missing STRATEGY_SUPPLY_SET_CONFLICT_ISO for combo cell
2832606 mismatch in the instance name between GUI and rule check report
2837250 enhancement to report LSH_REDUNDANT/1801_LSH_REDUNDANT when driver and receiver supply set are the same in pre-synthesis
2844526 run stops when lint failures during power intent elaboration
2845142 restrict ISO_EN_DATA_DRV_SUPPLY_DIFF_ISO_ASSERTION only to block level ISO/memory and driver
2845145 missing ISO_EN_DATA_DRV_SUPPLY_OFF_ASSERTION_MISSING violation during post_route analysis style
2852423 crash during 1801_SUPPLY_PG_PIN_CONFLICT rule check
2852698 "report_compare_grid" not using separate lines for golden and revised in some cases
2853321 command callback for "set_simstate_behavior" seems incorrect
2854737 "write_power_intent -1801" from lec results in 1801_LINT_REF_OBJ_NOT_FOUND when gol.upf is read back
2856215 crash at ISO_EN_DATA_DRV_SUPPLY_OFF_ASSERTION_MISSING rule check with "report_rule_check -lp -verbose -attr" command
2856298 set_related_supply_net power_intent compare filter not filtering
2858391 enhancement to report 1801_RET_CTRL_CONST check in Hier blackbox flow
2858392 enhancement to report 1801_HIER_BBOX_IN_CLAMP_CONFLICT with clamp values from isolation strategy
2858969 crash at "Identify pim graph pins connected to analog" check with 23.1.a301 build
2859072 crash during "read_power_intent"
2859760 crash during phase insertion-1 (3/5) stage
2866297 crash during v22 and v23
2871001 reporting implementable elements for each retention strategy in RTL run
2873775 documentation of 1801_LSH_REDUNDANT rule check
2840089 enhancement request to recognize effective NOR-ISO supply set
2862483 enhancement request to valid cells information for combo strategy and 1801_COMBO_CELL_UNAVAIL if combo cell not present
2880399 error in "read_power_intent" due to namespace
2881200 crash when entering GUI mode
2881651 internal error
2887424 LEC is crashing on "read_power_intent" command
2890174 false CPI NEQ
2891710 "report_rule_check -create_rule_filter_template" generates duplicated filter name
2897236 "report_crossing_path -through -gui" crash


Fixed CCRs for Conformal 23.2 ISR s200

LEC:

1047143 retime move limit reached - cannot increase in automatic flow
1049512 unreachable report
1083104 analyze datapath failed to spawn job
1124424 documentation for DC gates
1130150 cannot remodel clock-gating
1178434 false NEQ due to redundant logic
1178954 initial x seq optimization
1187074 "report_svf_info"
1203422 LEC violation when using integrated clock gating cell with Isolation
1225164 LEC older version causing false NEQs
1229653 crash while parsing VHDL file
1236665 reading mix SV and VLG
1252230 speed up hierarchical compare of datapath intensive designs
1255351 LEC mismatch with DC
1258991 incorrect inverted mapping phase identified by the tool leads to more noneqs and bigger patch
1260795 "add_ignored_outputs" Tcl command doesn't output warning messages, not consistent with vpx command
1262846 "add_primary_input -pin" not working on hier inst pin
1271097 module name with $variable
1272003 is there a way to view peak memory usage during a run?
1272021 "add_primary_input" to take multiple path
1308540 cTrace enhancement
1318181 "checkpoint" OS version and machine independence
1318185 "set_gui on" option to invoke mapping manager directly
1318187 LEC GUI preferences savings limitation in .lecguiinit and .confromal_gui.rc
1319275 dynamic hierarchical results reports NEQ modules EQ after flattening with older version
1324172 "read setup_info"- // Error: Cannot copy substring 2 (max 32k)
1330140 datapath aborts when using -module option
1337144 crash when comparing primary outputs
1337750 Tcl mode to report top module using "get_module_top"
1340431 enhancement to support "get_cells" Tcl command with filtering capability
1340433 enhancement of Tcl "get_pins" to support wildcards and filtering by instance names
1342209 Tcl equivalent commands in reference manual and user guide
1348878 "add_module_attribute -cpu_limit" is not honored during multi-threaded "analyze abort -compare" in older version
1350779 difference in number of X assignments between LEC versions
1351670 crash due to "abstract_gated_clock"
1368498 "restart_checkpoint" can not continue to resolving aborts with "read_setup_information"
1377452 diagnosis manager enhancement to show non-corresponding support key point type
1379940 "read_design -merge BBOX" does not work as expected
1393940 false seq constant
1397950 "analyze_abort" runs for days and never finishes, gets stuck on 8 abort points
1398621 'analyze project' and "set proj name -read_only" don't work after restarting checkpoint
1399180 request LEC command to load a gui configuration file
1399183 enhancement to echo/report current tool mode
1409379 crash
1410336 request to add process percentage when restarting a checkpoint
1416998 unsuccessful mapping multi_dimensional flops with structures to unidimensional
1418188 RC/LEC retiming guide needs update
1420047 "analyze redundancy" is not effectively using the cpu limit
1425107 multibit mapping incorrect
1435589 enhancement to support DP_csa_tree_* when CIGs pushed & retiming used
1435664 tab completion doesn't work correctly in GUI
1436587 crash when dumping the modeling messages
1438866 cannot change array delimiter in system verilog struct
1448821 "add notranslate module" parses the guts of the module; causing script abort
1449347 datapath aborts using resources report; wordlevel and "analyze abort" never finishes
1452240 enhancement for "set parallel option"
1453543 runtime improvement- runs for 6 days due to functional partition of abort modules
1466669 incorrect verilog code parsing causing false NEQ
1472825 discrepancy with automatic "add partition points"
1480548 automatic functional partitioning is skipped when datapath -wordlevel option is specified
1483047 incorrect system verilog parse error
1483430 false NEQ + merging issue
1483635 compare for extra feedthrough in-out and cloned outputs
1491169 set undriven signal did not effect to self-loop output
1495753 module not getting blackboxed
1496551 json mbit info is discarded; renaming rules are required
1501938 false error RTL7.16
1502449 enhancement to disable dynamic flattening at the toplevel
1504982 document update for the new options of "set multibit option"
1509294 enhancement request to add "get_project_name" to return project name
1511386 fixed size recursive coding
1514228 SV requirements, Default Port Value
1514256 SV requirements, Using begin-end to create local scope doesn't work
1515204 false SV3.2 Error
1518462 incorrect VHDL parse Error of "unresolvable expression"
1520810 elaborate design hangs
1521979 aborts on DP_OP due to low analysis quality
1522003 aborts on DP_OP due to low quality DP_OP analysis
1524243 parse error: The aggregate has incorrect number of members
1524345 Tclmode cannot show invalid message
1524579 How to Select Ideal value of Threshold for Reducing Runtime in LEC Runs
1525497 enhancement to control dynamic flattening at the toplevel
1525516 enhancement to show a message when using source rather than dofile in LEC
1525533 enhancement to drag and from object instance names to command line
1528423 unreachable points appear as Not-Mapped in mapping manager
1532038 variable index is out of the defined range
1533674 enhancement to "report compare data -concise -nolib"
1537468 "report key point" summary
1538648 incorrect mapping between G1G2 LEC leads to Extra Patch and standalone Patch verification Issues
1544316 incorrect interpretation of array of instances for synthesis, causes NEQs
1549604 NEQs
1554386 ECO does not find a Valid Patch
1555129 hierarchical dofile written by CFM errors out due to incorrect syntax
1557001 LEC hangs
1561207 LEC elaboration issue
1565756 request to support SDC style query commands similar to Genus and Tempus
1573244 ignore the force and release construct from the RTL model
1584969 learn MDP with inverted pin and bit blasted
1586379 extend "analyze gate" sequential constant source analysis to include all mapped pts and BBOXes
1587620 rtl2gate compare gets stuck for days; does not complete
1588779 LEC terminates during compare; memory utilization debug needed
1590316 enhancement to let "add renaming rule" be applied for the instances in the specified module only
1602110 checkpoint doesn't honor "set_screen_display on-noprogress"
1602512 compare results of instance/output/pin equivalences and/or sequential merge
1607306 "add renaming rule -pin_multidim_to_1dim" not working properly and giving false NEQs
1619582 fails to load checkpoint
1619664 encrypted SV design abort
1622965 build in pattern request
1622973 build in pattern request
1628765 library checking fail when switching cell position
1631529 RTL1.2 or RTL1.1 violation
1633432 need to read in multiple block level information file
1634280 need to take correct representative pin in hierarchical dofile
1635127 is there a way to flatten a multi-dim register struct?
1638826 support of DC multi-bit report through "read setup info" for multi-bit mapping
1644445 abnormal exit from tclmode
1656371 VHDL-2008 parsing error
1671662 enhancement to not report an error on SV "assume"
1673127 parsing RTL form loop cut
1685480 hung during run
1688654 Error: String overflow detected
1690808 support IES style verilog command file
1695823 verify set reset on condition
1709885 false NEQ
1719672 crash while reading the VHDL file
1720629 Smart LEC has more aborts and longer run time than standard flow
1720633 Smart LEC has more aborts than standard flow
1720653 run never finishes when using smart compare and smart instance
1721980 Smart LEC with parallel run runs longer than stand 4 threads
1726538 to_integer(signed) not correctly understood by LEC
1732511 wire resolution report message
1734118 incorrect RTL1.9 lint warnings due to explicit type cast
1736306 "read design" hangs due to physical cell extraction
1739510 crash
1745045 need to exclude combination loop breaker in "read implementation information"
1747062 unknown option "set verification information -nosetup seq_merge"
1752275 "go_hier" loops forever if module crashes
1754256 NEQ on ECO netlist
1771360 quotes not recognized as valid syntax by Conformal Custom
1781092 "read_mapped_points" core dump
1783574 internal error when running LEC on new design
1794856 crash during "read_design -gold"
1800228 incorrect RTL1.12 caused by use of struct in different module
1800427 huge runtime with "go hier_compare"
1814210 need to support "add module attribute -hier_compare" in "go_hier"
1818583 NEQs due to bad interpretation of Liberty equation
1827299 dump stack during elaboration
1829514 Conformal could not read uwire on SV
1829527 Conformal could not read #1step on SV
1831030 reduced for loop syntax support in SV
1833485 Tcl command leads to "error reading package index file …/pkgIndec.tcl"
1839905 LEC fails to successfully analyze DW02_multp using "analyze module"
1839969 document new "run hier_compare option -nodynamic_modules"
1849553 incorrect RTL 7.16 error
1860610 "analyze retiming" not able to match the the DFFs in retimed modules
1878938 Error: RTL19.4: Identifier is not declared
1883446 LEC is passing wrong simulation value for AOI gate in the schematic leading to NEQs
1894738 need to change DW_fp_exp.v parameter name
1906944 "go_hier" process failing due to License error
1911783 abort due to MDP low quality 35%
1923754 VHDL elaboration NEQ
1927983 Genus/Conformal are interpreting a parameter in a different way
1963412 optimize patch with option "noflatten_small" lead to HMUX module body duplication while doing next ECO
1982458 false HRC3.3 violation is flagged in CLP verify run
1994569 Elaboration fails with error "range of port is not a constant"
2007614 crash during "go_hier_compare"
2024692 LEC crashes if user tries to paste multiline command in GUI
2121247 Conformal 18.20-d327 fails but 18.20-d311 passes
2178393 enhancement request for tool methodology to handle cross boundary sequential constants
2337707 aborts
2419670 typical checkpoint size reduction
2460428 single GUI for all LPC (CPI\CPX\CPG\CPC)
2477916 fatal error on "report test vector"
2489935 checkpoint issue on SLES12 machine
2498576 RTL7.16 when array is declared after usage
2499855 crash in one pass flow with 21.1 LEC
2540194 need to issue Error message when RTL contains REAL data-type
2543682 abstract logic abort
2552436 Error: Reference to undeclared variable in module rs
2593238 NEQ
2617093 source diagnosis can show resource sharing operand in each condition
2618721 incorrect Error message about Interface being used before its declaration
2620045 BBOX NEQ
2622078 Genus Written dofile unable to write most of the modules during hierarchical compare
2622216 DLAT NEQ
2623957 NEQ with dofile written by "write_do_lec"
2635939 option to retain the escape character "\" in the instance pathnames
2653137 Genus RTL-map NEQ
2660227 abstraction logic not working
2671739 unable to read top level encrypted RTL
2681153 syntax error on SV attribute after macro usage
2681197 recent builds exit out with no message after read design command
2689458 crash
2689980 restoring a checkpoint failed without an indication
2693351 request "REPort DATapath REsource" in setup mode
2703871 "Add instance equivalences" makes second keypoint representative
2712577 crash during elaborate_design
2716805 Error: RTL7.6a
2717975 crash in running abstract logic
2723629 Error to be reported during reading of macro definition with repeated formal argument names
2730351 "find_cfm" returns incomplete list
2738120 incorrect E gate mapping causing NEQs
2744042 NEQ due to different understanding of the RTL between Conformal and Genus
2747731 enhancement of adding recipe in compare_recipe [DP0]
2747769 enhancement in compare recipe status
2749268 error with "analyze hier_compare" when "add module attribute" command is used for retiming modules
2751306 crash on Palladium synthesis checking
2755261 failure in LEC general retiming
2761332 "report_guidance_info -seq_constant" - flops are reported as unreach because they do not exist in the netlist
2761340 false NEQ without user merging
2765506 mapping file works when sourced, but not with "set analyze option -mapping_file"
2766150 "report_unreachable_gates" excessive runtime
2766275 request for non-global multiplier_implementation setting capability
2774787 NEQ due to failure in retiming
2775249 Conformal errors on concatenation in a function call in VHDL
2781951 abort resolution/runtime issue
2782901 request to have dofiles created which allow for standalone execution to reproduce issues
2785147 information and app notes on mapping commands
2788295 support for double forward slash in resulting path
2788859 add -outside_retimed_module switch to "get_unmap_points" and/or "report_unmapped_points"
2806829 crash during modeling
2810790 RTL-PnR merging not being done
2811757 MBF mapping not being done by name
Cadence Conformal technologies provide you with an independent equivalence checking solution enabling verification of designs from RTL to final netlists from P&R. In addition to standard equivalence checking, the Conformal solution offers:

- Static verification solutions for low-power designs, including low power-aware equivalency checking.
- Automated ECO generation capabilities for minimal netlist changes and faster tapeouts.
- Constraint designer for clock domain crossing and SDC verification solutions.

Introducing Conformal Smart LEC







See how you can achieve dramatic runtime improvement for logic equivalence checks.
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.

Owner: Cadence Design Systems, Inc.
Product Name: CONFORMAL (the former Verplex tool)
Version: 23.20.200
Supported Architectures: x86_64
Website Home Page : www.cadence.com
Languages Supported: english
System Requirements: Linux *
Size: 2.6 Gb


* System Requirements:


Supported Platforms
–––––––––-
Conformal products run on most major UNIX workstations.

X86_64 : RHEL 6 and 7 (64 bit) : SLES 11 and 12 (64 bit)

Supported Design Formats
––––––––––––
- Verilog (RTL and gate-level)
- System Verilog
- VHDL (RTL and gate-level)
- EDIF
- NDL
- SPICE (CMOS)

Supported Library Formats
––––––––––––-
- Verilog
- VHDL
- Liberty

    

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Cadence CONFORMAL 19.10.100

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