[行业软件]Cadence Design Systems Analysis Sigrity 2022.1 HF004 (x64) [复制链接]

Cadence Design Systems, Inc., a leader in global electronic design innovation, is pleased to announce the availability of Sigrity and Systems Analysis 2022.1 HF001 (22.10.100) is a supplier of software for IC package physical design and for analyzing power integrity and signal integrity.

Cadence Design Systems, Inc., a leader in global electronic design innovation, is pleased to announce the availability of Sigrity and Systems Analysis 2022.1 HF004 (22.10.400) is a supplier of software for IC package physical design and for analyzing power integrity and signal integrity.

Sigrity and Systems Analysis 2022.1 HF004 (22.10.400) Release notes - Date: 12-21-2022


Fixed CCRs: 2022.1HF4

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CCRID Product Title
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2726999 BROADBAND_SPICE S-parameter model checker: Passivity and causality report from any file
2718214 CELSIUS Mapping relationship issue occurs in the vertical .cfd file
2647312 CLARITY The airbox is different when using parametric import and non-parametric import in Clarity 3D Workbench
2653811 CLARITY Standard volume/surface seeding has no impact on mesh
2686605 CLARITY Clarity 3D Layout gets stuck in the AFS stage
2704441 CLARITY Clarity AFS0 is not efficient
2712819 CLARITY Optimality simulation stopped with an error for a 16 parameters case
2722868 CLARITY Clarity 3D Workbench quasi static solver succeeds in 3D inductance extraction but fails in sweeping mode
2731236 CLARITY S-parameter results are not correct for one signal net
2733867 CLARITY Parametric import in Clarity 3D Workbench does not preserve metal shapes
2734558 CLARITY Low frequency sweep is failing in Clarity
2741029 CLARITY Unnecessary license checkouts cause LMESH to fail on AWS using HF3
2729682 OPTIMIZEPI The EMI Optimization option remains disabled despite complete setup
2722499 POWERDC Applying the PowerTree topology in PowerDC does not complete the PowerTree application wizard
2728437 POWERDC Using the Tcl command DisplaNodesOnCircuitNodePads causes the GUI to exit unexpectedly
2728449 POWERDC The Tcl command DisplaNodesOnCircuitNodePads shows nodes inside vias
2709420 POWERSI Frequency sampling is incorrect from the DCfitted_customized model
2722007 POWERSI Capacitor model assignment error occurs in PowerSI
2723559 POWERSI PowerSI exits unexpectedly during shape processing
2734811 POWERSI DC_Fitted snp output file is missing in PDN Extraction using PowerSI
2693519 SIGRITY_SUITE Fanout routing moves to other layer when swept in Clarity 3D Layout HSSO flow
2706495 SIGRITY_SUITE XtractIM produces different mapping file starting from Sigrity2022.1 HF2
2727959 SIGRITY_SUITE Pad Stack window in PowerSI does not display correctly
2730550 SIGRITY_SUITE The port generation flow for multiterminal circuits in Clarity 3D Layout does not generate the S-parameter results
2730949 SIGRITY_SUITE Failed to check port connection error occurs in Clarity 3D Layout when the Cut & Stitch method is used
2737253 SPEED2000 SPEEDEM failed to read IBIS model
2682592 TRANSLATOR Pads are missing after translation
2741685 TRANSLATOR Change in padstack names when importing .tgz file into PowerSI
Systems Analysis 2022.1

Celsius Thermal Solver

- Viscoelastic Material Properties Added to the Material Manager: You can now define viscoelastic properties of materials to study the structural response of your design with respect to stress and temperature. In Celsius, viscoelastic properties are represented by the Prony series calculations, as per the following expression:
Where G0 is the instantaneous shear relaxation moduli, Gi is the Prony series coefficient, and τi is the relaxation time for each Prony component.
- Temperature-Dependent Dissipation Curves Added: You can now define temperature-dependent dissipation curves in the Celsius Solid Objects Simulation for 3D Structures and Celsius Fluid Flow Simulation modules. You can then use this curve data when specifying power for the static 2D and 3D heat sources.
- Plots Enhancements: The following improvements have been made in the simulation results plots in the Celsius Solid Objects Simulation for 3D Structures and Celsius Fluid Flow Simulation modules for improved usability
. All curve items are now plotted in different colors
. Curve results can now be exported to a .csv file using the Export CSV option in the context menu
. The scale of the plot axis can now be updated by double-clicking the axis and specifying new values for the X and Y axis
- Task Assistant Implemented for Solver Options Form: A new help tool called Task Assistant, has been implemented in the Solver Options form in the Celsius Fluid Flow Simulation module. Task Assistant provides a quick overview of the tasks in the context of the action you are currently performing. It provides help information for the possible "how to" questions that you would have in mind while setting up the solver options for a simulation run.
- Sweep Parameter Enhancements: In the Celsius Solid Objects Simulation for 3D Structures and Celsius Fluid Flow Simulation modules, the parameterization support has been extended to include other objects in addition to boundary conditions and material properties. The objects and boundary conditions that support parameterization are: Static Power and Temperature, Heat Transfer Coefficient (HTC), VRM/Sink Patch, Component Thermal Models, Surface and Volume Seeding, and Simulation Options. In addition, the Celsius Fluid Flow Simulation module supports the parametrization of Flow resistance, Chamber and Chassis Attributes, Fan (construction and cooling) Properties, Mesh Refinement, and Liquid Cooling.

Clarity 3D Solver

- New Meshing Algorithm Introduced: Clarity 3D Layout now supports a new meshing algorithm, LMesh. LMesh is much faster than XMesh and is specifically designed for layer-based structures (PCB, PKG, interposer/IC).
- Area Ports Enhanced: In Clarity 3D Layout, area ports can now be defined as horizontal lumped gap ports or coaxial ports. You can now also specify the distance between the positive nodes. If the distance between the two positive nodes is within the specified value, only one of them is used to create the port.
- Post-Processing GUI Developed in Clarity3DWorkbench for Better Visualization of the Field Quantities: For better and enhanced visualization of the field quantities, a new GUI is now available that enables you to perform operations, such as plotting on a slice, line, and points on the 3D objects and also plot multiple field quantities. All the capabilities from the legacy field plots have been transferred to the new post-processing GUI. The new post-processor can now handle large .R3D files and designs with ease and overcomes the GUI latency when changing the port or frequency, or performing any operation in the legacy flow.
- Support for Wave Ports Added in Clarity 3D Workbench: Clarity 3D Workbench has been enhanced to support wave ports. A wave port represents the excitation from a semi-infinite waveguide whose cross-section is the same as the wave surface. It is more accurate than a lumped port because the excitation field pattern is calculated from the cross section. As a result, it is closer to the real excitation and does not introduce any additional parasitic effect.
- 3D Component Updates: For the encrypted 3D Components the mesh and field results are now not visible for the hidden parts during post-processing in Clarity 3D Workbench. This helps vendor companies to protect their IP when sharing their components (such as 3D capacitors, 3D inductors, 3D connectors and off-the-shelf antennas) to hide the inner details of the design, but at the same time enables their customers to use the components and run the 3DEM simulations.

Sigrity 2022.1

Sigrity SPEEDEM

- S-parameter Simulation Methodology Enhanced : The S-parameter simulation methodology has been enhanced to reduce the run time. Depending upon the actual cases, performance improvement can be up as much as 50 percent.
- Sparse SPICE Circuits Algorithm Enhanced: The algorithm used in solving sparse SPICE circuits is enhanced by the new multi-threading architecture and matrix partition solver. It can help to increase the simulation speed of sparse SPICE circuits by two to four times.

Layout Workbench Enhancements

- Die Stack Functionality Added: Layout Workbench now supports the Die Stack functionality that lets you review and edit the die stacking information in a design. You can now view die stacking information, such as the attachment type, orientation, pad height, and placement sequence, in a design. In addition, this functionality helps you edit and view the thickness of the design on a real-time basis.

Sigrity and Systems Analysis 2022.1 HF001 Release notes - Date: April 2022

Release Highlights

Sigrity and Systems Analysis 2022.1 HF1
Note: The Sigrity and Systems Analysis 2022.1 HF1 release is largely focused on fixing existing bugs and offers a limited set of new features.

Documentation Updates

Products with no What’s New Information
No major enhancements that qualify to be listed in the What's New document were made for the following products:
- Clarity 3D Layout
- Clarity 3D Workbench
- Clarity 3D Transient Solver
- Celsius Thermal Solver
- PowerSI
- Broadband SPICE
- SPEEDEM
- OptimizePI
- T2B
- Translators
- XcitePI
- XtractIM
- PowerDC

To minimize these threats, compensate them and increase the quality of high-speed circuits, needs analysis and corrective actions that the software Allegro Sigrity it is convenient for us. The software combines technology with design, editing and routing IC and PCB coordinate Cadence® Allegro® enables advanced analysis of both pre-layout and post-layout provides for users.

The software is designed to examine various scenarios in the initial phases allows accurate design and redesign minimized. This software supports reading and writing directly on the PCB and IC design of Allego's database. Accurate simulator based on SPICE as well as built-solver for 2d and 3d extracts the user. The software also modeling the transistor-level input and output functions include power-aware IBIS 5.0 support.

Features and Applications Allegro Sigrity:
-Perform a wide range of SI analysis or Signal integrity (signal integrity)
-Early detection of design errors to increase success in the early phases
-Restrictions can be set quickly and accurately apply the basic processes
-Improve product performance through exploration and space solutions
-Evaluation of alternative topologies in infancy
-Production of S parameters of the topology and signal analysis in the form of parameter S
-Tables estimate interference designed to increase productivity
-Was approved after PCB design and IC design directly on boards
-Multiple evaluation and confirmation signals for different paths on silicon boards

Interconnect Modeling Technology
-Upgraded interconnect modeling technology addresses latest trends on PCB and IC package design.With signal speeds climbing to 32Gbps and faster, the need to strategically model PCBs and connectors as one structure is now required. The new Cadence® Sigrity™ 3D Workbench, included with the Sigrity PowerSI 3D EM Extraction Option (3DEM), allows users to import mechanical structures, such as cables and connectors, and merge them with the PCB. This way critical 3D structures that cross from the board to the connector can be modeled and optimized as one structure. Updates to the PCB can be automatically back-annotated to the PCB layout tool.

The 3D Workbench offers:
-SI and PI applications
-A familiar 3D look and feel
-Ability to import mechanical structures
-Ability to import electrical databases and merge with mechanical structures
-3D solid modeling (parametric and full featured)
-Simulation of
-Twisted pair wiring (cables)
-Backplane plus connectors
-Connector modeling (HDMI, SATA, etc.)
-SMA connector on a PCB

Rigid-Flex Support
Industry-first full Rigid-Flex PCB extraction from a single layout database provides accurate interconnect modeling of both rigid and meshed-ground flex cable zones. The zone information is automatically imported from version 17.2 of Cadence Allegro® technology.

Faster IC Package Modeling
-IC package modeling of designs with thousands of bumps/balls is now 3X faster and memory consumption has been reduced by 75 percent.

Power Integrity Updates
-Upgraded power integrity (PI) technology addresses new checking requirements and new usability requirements for PCB front-to-back design flows. Many enhancements have been added, including hierarchical views, quick search, and filtering, comparison tree report, and tool tips.

Allegro PowerTree™ technology
-The DC analysis technology has been upgraded to support integration with Allegro technology, HTML block-diagram enhancements, and automated add-nodes-on-pads enhancements.

Sigrity PowerDC™ technology
-The AC analysis technology has added some additional checks that now look at the weighted AC current and checks for equal voltage. New batch-mode “projects” allow these two new workflows as well as others to be setup as a set of batch checks.

Sigrity OptimizePI™ technology
-Upgraded signal integrity (SI) technology accelerates the time it takes to verify memory interfaces, serial links, and the plethora of other signals on a PCB that can cause a design to fail in the lab. The technology now features workflows and visions that can be used to quickly perform electrical rule checks that find impedance variations and excessive coupling. These checks require no models and can be run by both expert and non-experts in signal integrity.

System Requirements:
OS:Windows 10, 11 (64-bit), Windows 2012 Server (All service packs), Windows 2016 Server (All service packs).
Note:Note: Clarity 3D Solver and Celsius with Hyper-V are not supported on Windows 7.
CPU:Intel® Core™ i7 4.30 GHz or AMD Ryzen™ 7 4.30 GHz with at least 4 cores
RAM:8 GB RAM / 64 GB RAM or higher
Space:50 GB free disk space / 500 GB free disk space SSD is recommended for primary operating system (OS) and simulation working directory
Internet:Microsoft® Internet Explorer® 9.0 or later
Display:1,024 x 768 display resolution with true color (16bit color) / Large monitor (or two) with Full HD resolution or higher
GPU:Dedicated graphics card with 1 GB video memory or higher

Home Page - https://www.cadence.com/

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Cadence Design Systems Analysis Sigrity 2022.1 (x64)

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