[行业软件]Cadence Virtuoso Studio IC23.10.060 linux [复制链接]

Cadence Design Systems, Inc. announced the new Cadence Virtuoso Studio IC23.10.060, a next-generation custom design platform that delivers an optimal design experience and ushers in the future for custom analog design.

Cadence Unleashes the Future of Analog, Custom and RFIC Design with Pioneering AI-Powered Virtuoso Studio

Highlights:
- Industry’s leading platform for creating differentiated custom silicon delivers unmatched productivity benefits with new generative AI technology
- Virtuoso Studio empowers designers to push semiconductor and 3D-IC design boundaries by seamless integration with Cadence’s cutting-edge technologies and modern infrastructure
- Leverages 30 years of industry leadership for all process technologies enabling 3X productivity improvement for today’s largest designs that will shape the world of tomorrow

Virtuoso Studio features a reimagined infrastructure with a unique approach to managing design processes and allows more than a 3X improvement in design throughput for today’s largest designs, enabling customers to meet aggressive time-to-market goals.

Virtuoso Studio addresses the challenges customers face with larger, more complex designs, empowering them to analyze and verify designs to ensure that design intent is maintained throughout the design cycle. This new platform features seamless integration with other Cadence solutions, including the Cadence Spectre Simulation Platform, Cadence Allegro PCB Design and Cadence Pegasus Verification System, removing traditional barriers between different design domains and speeding design closure. Virtuoso Studio is newly integrated with the AWR® Microwave Office solution, and the Pegasus Design Rule Check (DRC) Solution and Layout Versus Schematic (LVS) Solution are now available from within the Virtuoso Layout Suite. These provide advanced mmWave design and interactive signoff quality analysis during layout creation. Additionally, customers can access the Spectre Simulation Platform, including the Spectre X Simulator and Spectre FX Simulator, through Virtuoso Studio, which allows for the analysis of the industry’s largest analog and mixed-signal designs.

The new Virtuoso Studio platform offers customers the same great experience they are accustomed to, with the following benefits to address growing complexity:

- Proven Solution: Virtuoso Studio continues to offer the secure, proven solutions that industry-leading companies and foundries have trusted for 30 years for their analog, RFIC and mixed-signal designs.
- Improved Productivity: Design teams can leverage comprehensive planar and FinFET-based layout placement automation and new routing solutions to improve engineering productivity.
- Cloud-Ready: Virtuoso Studio offers massively scalable, cloud-ready solutions for occurrences when hundreds of simulations turn into thousands. It is optimized for customers’ preferred cloud providers or ready for private cloud deployment.
- Generative AI for Design Migration: The foundry-supported solutions ease the burden of process migration for schematics and layouts. Tools within the Virtuoso ADE Suite quickly re-center and validate designs post-migration, so customers can achieve aggressive time-to-market goals. Customers can utilize the AI-enabled tools to take existing IP and transform it for their next-generation designs.
- 3D-IC Integration: Virtuoso Studio allows the heterogeneous integration of 2.5D and 3D designs for advanced nodes, analog/RF packaging/modules and photonics systems.

Virtuoso Studio stays at the forefront of delivering designs accurately and on time through innovative improvements in traditional custom design tools. The new Design Space Optimization feature lets customers utilize AI algorithms to navigate competing specifications and aid in design centering, particularly after the process migration of a design. Customers can experience faster interactive editing in both the layout and schematic tools, thanks to optimized code and algorithms, while multi-threading accelerates rendering, connectivity extraction and design rule checks in parallel. Additionally, the Cadence Spectre FMC Analysis is integrated into Virtuoso Studio and provides a complete machine learning (ML)-based Monte Carlo variation solution to deliver a 3-to-6-sigma yield with orders of magnitude speedup over brute force Monte Carlo analysis.



CCRs Fixed in Virtuoso Studio IC23.1 ISR6 (April 2024)

CCR
Number TITLE

2961954 Virtuoso Studio exits unexpectedly when changing a test name in Virtuoso ADE Assembler
2959667 Only layers selected using the Filter icon on Voltus-XFi Results Browser should be plotted
2958326 The Choosing Analyses form lets you define measurements for sampled(jitter) noise type only for the last test in the setup
2957260 calcVal wizard: Cannot edit the function expression because the expression is no longer selected in buffer
2955624 Virtuoso Studio exits unexpectedly while updating CDF parameter of Pcell
2955525 Virtuoso Studio exits unexpectedly when changing a test name in Virtuoso ADE Assembler
2955521 Virtuoso Studio exits unexpectedly when copying a test name in Virtuoso ADE Assembler
2955289 Virtuoso Studio exits unexpectedly while running standard Monte Carlo simulation in LSCS mode
2955272 Consider insideLayers for minSpanLengthSpacing to allow proper minimum spacing for create bus
2954128 Virtuoso Studio exits unexpectedly when the Batch Checker is run using the Check Constraints button in Constraint Manager
2953960 Standalone Abstract Generator has missing text in the menu
2953161 Auto Place and Route Create Group command exits unexpectedly when modgenCreatePreserveLayout is set to t
2952818 Virtuoso Studio exits unexpectedly after a new job policy is created during simulation
2952533 Virtuoso Studio exits unexpectedly in IC23.1 ISR4 and ISR5
2952294 Unnecessary Smart Views are created when using Pegasus/Quantus setup for parasitics extraction
2950333 Unable to create voltage constraints if testbench schematic and design under test schematic have different view names
2949632 Wire Extender Fixer issues warning: No minSideSpacing rule with exactAlignedSpacingRange parameter
2949346 Update Binding using PVS LVS .ixf and .net files creates complex bindings and unbound instances
2948633 Manually stopping FMC run does not exit the Spectre worker processes
2948217 A false error is reported about selection of missing instTerms when using a view name other than schematic
2948141 Virtuoso Studio exits unexpectedly after reporting the error ASSEMBLER-2225
2947913 Virtuoso Studio stops responding when routing two nets
2947766 The Save icon appears dimmed after making changes in the Corners form in Virtuoso ADE Assembler
2947366 Voltus-XFi Results Browser shows SHE results even when SHE is inactive
2947219 Inconsistent instances in the schematic because the Replace form did not run callbacks
2947161 Skip the LEFDEF_MANUFACTURINGGRID check because the mfgGrid definition already exists within the PDK
2946436 Remove PVS-CV dependency from Constraint Manager Check Constraints button to run constraint validation
2946033 Unable to preview WSP
2945965 The Merge command deletes shapes when running with the non-savable ruler selected
2945759 Internal error in the viaAutomaticToolbarCL::autoViaInEntireCellviewEF function when generating via with the Auto Via Assistant
2945752 How to reset XY zoom after pressing the bindkeys 'x' and 'y'
2945222 License options are not added to runSimulation when using Spectre FX
2944856 Exporting results data to Microsoft Excel does not work if the background export script has incorrect settings
2944623 The Update Components and Nets command yields incorrect device counts and results
2944583 Virtuoso Studio exits unexpectedly after a new job policy is created during simulation
2944258 The Highlight Dummy Fills command highlights dummy cells and Modgens
2943749 Virtuoso Studio stops abruptly while creating an extracted view
2943713 A few multi-patterning technology colors are missing from the ?maskColor argument of abeBlockagesFromCellView
2943165 Spectre monitors do not end when using Simulation Manager
2943055 IC + Package: bumps not generated if pin name contains < and > (digital bits)
2942563 LSCS simulations stop responding during netlisting stage and report a syntax error if special characters are used in output expressions
2942119 Instance is not netlisted when running CDL Out in flat mode
2942033 Eye mask fails even when the eye mask is confined within the eye
2940866 The Max Coupling Capacitance constraint is not checked when using Pegasus/Quantus setup for parasitics extraction
2940844 The Max Coupling Capacitance constraint is not checked when using Pegasus/Quantus setup for parasitics extraction
2939375 Virtuoso Studio exits unexpectedly during the CDL Out flat netlist
2939009  Use the vdspf generated by EAD Resimulation flow for netlisting and simulation in Virtuoso ADE Assembler
2938822 The showNoiseSummaryInTableWidget environment variable generates incorrect noise summary report after corner simulation
2938551 The Copy or Move command does not update the via and metal enclosures when the snapResizeWireObjects option is selected
2938539 Performance issue when running Generate All From Source if the cell has a constraint view
2938484 Virtuoso Studio exits unexpectedly when running the maeAddRelxSetup function
2938323 Virtuoso Studio exits unexpectedly [readSignalPackages]
2938149 The Check Hierarchy command leaves schematics with errors open for append
2938067 Eye mask passes the check even for the signals that do not meet the eye mask dimensions
2938055 EAD resimulation must run irrespective of data in the layout cellview
2938054 Net information is not updated in the EAD Browser when a net in the design is created or deleted
2937853 Request to update layout binding using LVS database
2937787 Issues when opening the same maestro cellview in two Virtuoso Studio sessions
2937511 Multiple syntax differences occur between netlisted variables
2937415 Virtuoso Studio exits unexpectedly when modifying a marker label
2936998 No log is generated when Virtuoso Studio exits unexpectedly
2936856 The cell names for row previews in the Row Template Manager must support additional prefixes to prevent conflicts during access
2936556 Health Monitor in Virtuoso Studio is not working in the customer setup
2936001 Spectre AMS Designer simulations stop without a message when SimVision MS Debug is used with Spectre FX
2935989 Delete failed nets to remove metal shapes added together with trim shapes in device-level routing
2935770 Virtuoso Studio exits unexpectedly when modifying a marker label
2935249 Virtuoso RF Solution: bumps not created when using Virtuoso Studio IC23.1 and Clarity 3D Solver 23.1
2934917 The maeCreateNetlistForCorner SKILL function incorrectly prints dependent parameters in quotes
2934805 Some DRC violations remain with the new shield router
2934751 Virtuoso Studio exits unexpectedly when extracting dummy width information from a device in the extraction group
2934662 Power and ground net shorts are reported in Abstract Generator
2934612 Virtuoso Studio stops responding when adding net 'vss' to EMX model in large design
2934351 Mesh router fails to follow user-defined meshCount even when the meshExtendToMeetCount environment variable is enabled
2934055 LVS Flow Multiplied Instances: PDK model instances erroneously kept in stitched Smart View
2933915 Iterated instances are not stitched or connected correctly to nport instances in Smart View
2933783 Check Against Source reports a mismatch in die thickness between the layout and schematic views
2933169 Virtuoso Studio exits unexpectedly when changing a test name in Virtuoso ADE Assembler
2932907 Base view of the imported .sip/.mcm file shows blank unless zoomed in
2932790 Pin to Trunk feature of device routing creates a broken trunk causing an open net
2932741 The mesh route feature of device routing creates Via-to-Via spacing DRCs
2932730 Pin to Trunk feature of device routing creates DRC violations in Cut Metal0 and Metal0
2932685 The filter for the Point column in the Detail - Transpose view is not working for FMC results
2932347 A false error is reported for selection of missing instTerms when using a view name other than schematic
2931842 Cannot add second jitter measurement in the Choosing Analysis form for pnoise analysis
2931049 Operating Point Parameters Summary report must support third-party simulators
2930546 Cannot change the aspect ratio in Modgens after user-defined groups are created
2930052 Virtuoso ADE Assembler displays an error when adding a tab in a SKILL expression
2930016 Iterated instances are not stitched or connected correctly to nport instances in Smart View
2929994 Design Intent-related warning or error messages from the Check and Save command are not displayed by Schematic Editor
2929987 Die pads do not shrink after an assisted export of a die instance with shrink factor
2929874 Assisted Import fails if .sip file is a link to a read-only file and of data type MCM
2929492 Histories are not synchronized when simulation is run on a maestro view that is opened on different machines in read-only mode
2929373 Filtering by 'degradType' does not work in Reliability Report view
2928691 Add an option to start the maximum number of implementations per batch before considering the maximum number of batch runs
2927508 Add accelerator keys to all buttons on the Schematic Find form
2927162 The Initialize step in the Auto P&R assistant takes more time in Virtuoso Studio
2926557 Assisted Export disables the Dynamic fill option in the generated SiP file
2926544 Problem with pnoise measure setup form
2926019 The Save icon appears dimmed after making changes in the Corners Setup form in Virtuoso ADE Assembler
2925910 In Application Readiness Checker, LVS does not bind schematic instance names of standard cells with square brackets
2925628 When trim insertion is enabled, device router creates CM0A/CM0B trim shapes in the entire layout and not just the routing area
2925518 No option available in Virtuoso ADE Verifier UI to specify Simulation Manager
2925210 Unable to specify Simulation Manager through job policy in Virtuoso ADE Verifier
2925090 In the Select Master form, the OK button is not working as expected
2924970 DRD is not checking hierarchical shapes when drdEditBatchHierDepth is set to 32
2924944 Device router inserted an extra trim layer causing DRC errors
2924632 LRP reports generated using the XPDB flow are different from the DSPF flow in Spectre 23.1
2923735 Template files are not created for all the devices present in layout while capturing data
2922661 A false error is reported about selection of missing instTerms when using a view name other than schematic
2922139 Pcell Designer exits unexpectedly when clicking Cancel
2921597 Incorrect rotation of via when performing hierarchical Yank/Paste operation using edit-in-place
2921574 Incorrect license checked out when using the viaGenerateViasAtPoint SKILL function in Virtuoso Layout Suite MXL
2920519 When abeLayerSize is set to a negative value, the resulting shapes differ based on the orientation of the polygon
2919464 Virtuoso Studio stops responding when ciHierarchicalSeriesIterator is called in a design with a large number of Pcells
2919420 The viaAutoViaInterface::createFromFigs function does not generate the via successfully when many shapes are set as input
2915742 Router leaves one pin open even though it does not cause any DRC violation
2915461 Certain nested expressions are not evaluated correctly
2913760 Missing port on VNCAP when parasitic blocking is enabled
2912548 The Selection Protection feature of Layout XL is not working with Virtuoso Chip Assembly routing
2910996 How to create a constraint that evaluates an expression with a template selected in the Constraints browser?
2910948 Width setting in shielding constraint is not being used when creating shields
2910686 An incorrect off-grid port is created in the EM Flow
2909810 Virtuoso SystemVerilog Netlister creates the cds_globals.sv file but the option -top cds_globals is missing from the xRunArgs file
2908780 Context-aware SRMS relaxation does not work for the Self-Heating Effect RMS analysis flow
2907231 History name in results are not sorted from the oldest to the newest or alphabetically
2907141 AMS UNL Netlister must report an error when a SPICE text cellview is instantiated in a Verilog-AMS view
2907139 spiceModels.scs file not included in xrunArgs when a SPICE text view is instantiated in a Verilog-AMS view
2906826 Supply Route does not lock cutlayer colors of via4 causing DRC violation with net after nano routing
2905768 Device router is not using width setting of shielding constraint in Routing Constraint Manager when creating shields
2904620 Virtuoso Studio exits unexpectedly when creating a new configuration
2904271 Performance issue with SDR because syncFromOA takes time to respond
2903937 During logical tracing, Net Tracer traces instance pin connection instead of top-level connectivity
2903690 The dependent fields are not updated in Multi-Test Editor
2900741 Missing port on VNCAP when parasitic blocking is enabled
2900146 Need Auto Via assistant to provide candidate vias even when the via stack depth is larger than one
2896379 Extra metal resistor found in the stitched Smart View
2887809 Overextension tandem shield with tandemSplitFull is generated by advanced shield router
2887795 Unnecessary tandem cap shield with TandemSplitSpecial is generated by advanced shield router
2886570 Unable to retrieve label for a hierarchical mosaic instance using dbGetTrueOverlaps
2882770 Issue with editing the cut pattern of multiple selected vias in the Edit Properties form
2881430 Virtuoso ADE Assembler must prevent deletion of a history if it is still in use in the current session
2881388 Configuration traversal is generating incorrect output for sub configuration
2880979 Virtuoso RF Solution: Incorrect computed boundaries for Clarity 3D Workbench
2878218 The emirreport log file must be created at the location given by Spectre through the -log command line option
2876169 Cross-fabric net trace does not highlight all layers of traced net in die instance
2855355 CDL Out is not reading top cell name from template while exporting CDL netlist
2852499 libImport creates shapes on a nonexistent later-purpose pair 'assemblyBoundary boundary'
2846930 Flatten: shapes move when flattening several levels of hierarchy at a time
2846660 Net Tracer edit-in-place is causing shifted halos from origin when tracing if subcell is open at same time
2846282 calcVal fails with debug level 3, works fine with debug level 2
2843499 An issue occurred while performing lef2oa conversion
2833794 Virtuoso ADE Verifier simulations are not working when verification spaces are assigned to custom requirements
2813949 Instance-based registration does not work as expected when stacked transistors are present in native isolation cell
2786554 Incorrect instance current reported in the post-simulation results for Smart View
2778732 libImport should create prBoundary shapes using ASSEMBLY_TOP/BOTTOM if BGA does not have PLACE_BOUND_TOP/BOTTOM
2763751 The Create New Point-To-Pont Info Balloon icon is unavailable in read-only cellviews
2668064 Hide Virtuoso Visualization and Analysis XL window when viewing the waveform results in Voltus-XFi
2595249 Smart View netlisting fails with error (PARA-3001) if the extracted design contains incorrect connectivity information
2578693 A file name passed to the instance of a Verilog-A model works as expected only when a single corner is used
2298397 The corner name does not appear for a file name when using the axlGetCornerNameForCurrentPointInRun SKILL function
537580 Search and Replace commands in Schematic Editor do not trigger CDF callbacks

April 2024

Cadence Virtuoso Studio leverages 30 years of industry knowledge and leadership in custom/analog design to give you broader support for systems, including RF, mixed-signal, photonics, and advanced heterogeneous designs. Innovative artificial intelligence (AI) techniques, cloud enablement, infrastructure improvements, and integration across Cadence products complement these design flows, creating a hub for efficiently delivering real designs for the real world.

Virtuoso Studio: Custom Design for the Real World







The analog design world we know is evolving. And so is Virtuoso technology. Learn how the best analog tools just got better to help you keep pace with your challenging design issues. The AI-powered Virtuoso Studio custom design solution provides innovative features, reimagined infrastructure for unrivaled productivity, and new levels of integration that stretch beyond classic design boundaries.
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare.

Owner: Cadence Design Systems, Inc.
Product Name: Virtuoso Studio
Version: IC23.10.060 Hotfix
Supported Architectures: x86_64
Website Home Page : www.cadence.com
Languages Supported: english
System Requirements: Linux *
Software Prerequisites: pre-installed Cadence Virtuoso Studio IC23.10.000 Base and above
Size: 9.6 Gb



* System Requirements:

          

    

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