Gowin EDA (FPGA Designer) 1.9.10 | 1.0 Gb
Gowin Semiconductor Corp., an innovator of programmable logic devices, announces the release of Gowin EDA 1.9.10.01 , is easy to use integrated design environment provides design engineers one-stop solution from design entry to verification.What's new in Gowin EDA 1.9.10.01The V1.9.10.01 release includes features and enhancement functions of Gowin Software. GOWINSEMI recommends downloading this version to get the latest software.Note！When programming GW5AT-LV138FPG676A, GW5AT-LV138PG676A, GW5AT-LV138PG484A sample, and creating a new project, you need to select the corresponding GW5AST-138 Version B PN to generate the bitstream file, and select the GW5AST-138 Version B device in Programmer. The following table summarizes the release items:New Functions
- IPs added: MJPEG Decoder, SerDes RoraLink 8B10B, MULTACC
- Supports GVIO
- Configuration option "VCC" added in IDE interface
- IDE supports third-party editor navigation and jump function
- tcl command open_project added
- For GW1N-2 devices, primitive TLVDS_OEN_BK added and read back supported when MIPI OBUF configured in LP mode
- GW5A(T)-60 and GW5A(N)(R)T-15 devices support Slew Rate setting
- Programmer adds "GoConfig IP Mode" function to support JTAG low-to-high speed debugging for LittleBee Family devices
- Programmer adds the function to generate SVF files through "exFlash Erase, Program thru GAO-Bridge 5A" and "exFlash Erase, Program, Verify thru GAO-Bridge 5A"
- "Analyzer viewer" interface added under the Tools menu in Programmer to be used to determine the current status of the device based on status codes
- The command-line version of Programmer adds "Embedded Flash Background Mode" function, which supports GW1N(R)-9C, GW1N(R)-9, GW1NRF-4B, GW1N(R)-4B, GW1N(R)-4D, GW1N-4C, GW1NS(R)-4, GW1NZ-1(C) devices
Updated
- IPs updated: MULTACC, DLLDLY, DVI RX, DVI TX, HyperRAM Memory Interface external, SPI Nor Flash Interface(With Internal Flash), MIPI_DPHY, FP Sqrt, SerDes USB 3.0 PHY, UHS PSRAM Memory InterfaceV2.0, FOC Current Loop Control Light, XCORR, EDP Decoder, EDP Encoder, EDP RX Desteer, JESD204B
- The Bank Vccio for MIPI Output updated to1.8/2.5/3.3
- True LVDS PULL MODE for 22nm devices updated to support NONE/UP/DOWN/KEEPER settings
- BSRAM timing data for 22nm devices updated
- Clock tree timing data for 22nm devices updated
- Timing data for GW1NZ-2 and GW1NZ-1 updated based on different VCC values
- "SRAM Program JTAG 1149" function in Programmer optimized to add support for Arora V devices
- "Write" function in the "Security Key Setting" interface in Programmer optimized by adding key verification to ensure the correctness of the key
- "exFlash Export thru GAO-Bridge" and "exFlash Import thru GAO-Bridge" functions in Programmer optimized to determine the read size based on the input address instead of a fixed size
- The write function of "jtagserver.exe" and "jtagserver_u2x.exe" in Programmer optimized to adapt to GVIO tool
- The stability of "Set Flash QE For 9x/18x" function in Programmer optimized
Not Supported
- No longer support reading initial value of BSRAM for GW5A(N)(R)T-15 A devices
- No longer support SSRAM for GW5A(S)(T)-138 B, GW5AT-75 B, GW5A(S)(R)-25 A devices
- No longer support DPB/DPX9B read before write mode for GW5A(R)(S)-25 A devices
- No longer support reading initial value of BSRAM GW1N(R)-4(B), GW1NRF-4B devices
- GW5A(S) (T)-138, GW5A-25 devices do not support GPA, power report, and IBIS file output currently
- IP Core does not support SDP36KE initial value configuration for GW5A(S) (T)-138 devices currently
Gowin design system is an integrated circuit design and implementation tool specifically for Gowin FPGA chips, and it has superior performance and easy to use. Gowin design system provides a comprehensive and optimized design for Gowin FPGA chips with the low-power and low-cost architecture, and it integrates the flow from RTL description to FPGA bitstream file generation, including design optimization, automatic design, and graphical interaction.Gowin EDA is an easy-to-use integrated design environment, providing design engineers with a one-stop solution. The complete GUI based environment covers FPGA design entry, code synthesis, place & route, bitstream generation, download, and online debugging of Gowin FPGA’s on customer’s boards. Gowin and Metrics team up to revolutionize EDA simulation - Dsim Cloud Webinar Gowin's Danny Finisher and Metrics 's Joe Costello (best known as the 1st CEO of Cadence Design) give an overview on a new cloud based FPGA design methodology. Followed by a step by step demo of DSim Cloud. Join us as we highlight why Gowin is excited to partner with the world’s first full feature, cloud-based simulator that supports SystemVerilog & VHDL design languages.Founded in 2014, Gowin Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation world wide with our programmable solutions. We focus on optimizing our products and removing barriers for customers using programmable logic devices. Our commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGA on their production boards. Our offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. We strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide. Owner: Guangdong Gowin Semiconductor CorporationProduct Name: Gowin EDAVersion: 1.9.10Supported Architectures: x64Website Home Page : http://www.gowinsemi.com.cn/Languages Supported: englishSystem Requirements: Windows & Linux *Size: 1.4 Gb * System Requirements: 本部分内容设定了隐藏，需要回复后才能看到
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