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[行业软件]Cadence SPB Allegro and OrCAD 2023 v23.10.008授权 [复制链接]

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只看楼主 倒序阅读 使用道具 楼主  发表于: 2019-10-21 17:30:11 , 编辑

Cadence SPB Allegro and OrCAD 2023| 8.0 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, is pleased to announce the availability of Cadence PCB Allegro and OrCAD 2022 HF8 (22.10.008) families of products aimed at boosting performance and productivity through improvements features and big fixed issues.



Fixed CCRs: SPB 22.1 HF008 - Date: 01-19-2024

=========================================================
CCRID Product ProductLevel2 Title
=========================================================
2796563 ALLEGRO_EDITOR 3D_CANVAS 3D Rendering of layers appears incorrect.
2802922 ALLEGRO_EDITOR 3D_CANVAS Lines on SURFACE FINISHES / CARBON_BOTTOM not displayed in 3D Canvas
2862872 ALLEGRO_EDITOR 3D_CANVAS 3D Mapper rendering issue
2877216 ALLEGRO_EDITOR 3D_CANVAS (SID: 54647) Shape on BOARD GEOMETRY - SILKSCREEN_TOP displayed on 3D Canvas incorrectly?
2890683 ALLEGRO_EDITOR 3D_CANVAS Allegro Crash when user click on "OK" or "Apply" in Preference window in 3D Canvas
2820734 ALLEGRO_EDITOR ARTWORK Context-sensitive menu issue in Japanese environment of OrCAD PCB Editor in release 17.4-2019
2847775 ALLEGRO_EDITOR DATABASE Warnning message in Allegro 22.1: This design has been modified using the Cadence X AI engine and and cannot be saved
2849582 ALLEGRO_EDITOR DATABASE Netlist import doesn't finish
2884980 ALLEGRO_EDITOR DATABASE Unable to open board created in 17.4 and tool getting crashed
2811667 ALLEGRO_EDITOR DFA DFA Table in CM does not accept 1.0x values
2853309 ALLEGRO_EDITOR DFM DFF Minimum Shape Width (positive) not flagging violations for shape widths smaller than rule
2878246 ALLEGRO_EDITOR DFM Design have alot of fasle uvia hole 2 uvia hole same net DRC
2882540 ALLEGRO_EDITOR DXF DXF export functoin changes after SPB17.4_S026
2872449 ALLEGRO_EDITOR EDIT_ETCH Timing vision is bugged once "Enable Static Phase at Vias option" is enabled.
2593126 ALLEGRO_EDITOR GRAPHICS Shapes not highlighted when using "Reject" in GPU-mode (Linux).
2724555 ALLEGRO_EDITOR GRAPHICS SOV highlight displays odd behavior
2872564 ALLEGRO_EDITOR GRAPHICS part of bundle flow not visible while in GPU mode
2894603 ALLEGRO_EDITOR GRAPHICS Color assignment to bundles not working properly
2907764 ALLEGRO_EDITOR GRAPHICS Program Crash in GPU mode
2805884 ALLEGRO_EDITOR MCAD_COLLAB Shape subclass changing after importing IDF file
2880362 ALLEGRO_EDITOR MCAD_COLLAB IDF Import on Flex design with zone using Multi cross-section swaps symbols shapes incorrectly
2862778 ALLEGRO_EDITOR PULSE Failing to migrate a DE_HDL/MMD based design into a Pulse managed MDD based board
2805010 ALLEGRO_EDITOR SHAPE Slide of arc segment for a shape uses last pick and not arc/circle center to use ix/iy easily
2879140 ALLEGRO_EDITOR UI_FORMS form_user_size env variable impact UI of Allegro Menus
2863683 ALLEGRO_EDITOR UI_GENERAL axlUIMultipleChoice - giving wrong return value upon escape/cancel
2865591 ALLEGRO_EDITOR UI_GENERAL axlDMDirectoryBrowse - "Directory:" field prefilled and "Choose" button disabled
2865778 ALLEGRO_EDITOR UI_GENERAL Include user env setting to auto clear search string in find by name textbox when enter is pressed
2866911 ALLEGRO_EDITOR UI_GENERAL “Paste” does not work in the SKILL (set telskill) window (SPB22.1 HF6)
2865644 ALLEGRO_EDITOR VIA_STRUCTURE Issue with eXML file generation for high-speed via structure in Allegro
2882923 ALLEGRO_EDITOR ZONES PCB Editor abruptly closes after DRC update
2893834 ALLEGRO_EDITOR ZONES Allegro PCB is crashing often randomly for unclear reasons and now the dbdoctor is crashing on brd file
2876619 APD DEGASSING Metal usage report is causing APD to crash
2881864 APD DEGASSING DXF export fails with "dxf_out exportlinesasshapes YES"
179822 APD DRC_CONSTRAIN Enhancement for custom Constraints between Padstacks
1990562 APD DRC_CONSTRAIN Additional parameter in padstack editor to differentiate via options
2591954 APD DRC_CONSTRAIN The new rules item for checking among BBvia structures in the same net spacing
2801475 APD DRC_CONSTRAIN Enhance ConsManager to support via classes defined by padstack type with different constraint values between classes
575104 APD DRC_CONSTRAIN Allegro can set spacing from differentiate test vias to other elements.
2863469 APD EDIT_ETCH Very slow performance of sliding a trace and delay tune (No shapes)
2876179 APD INTERACTIVE Netin crashes on the attached design
2888044 APD OTHER Bring back "icp_allow_dietext_flip_die to allow customer to use "flip placed symbol" in die text-in wizard
2865593 APD SHAPE Adding fillet to uVia doubles the uVia-to-shape SN spacing
2882751 APD SHAPE When running Update Shape, the dynamic shape is voided with incorrect clearance
2867199 APD STREAM_IF Missing degassing holes on GDS file
2877139 APD STREAM_IF Pad Degassing not showing correctly in the stream out file
2866861 APD UI_GENERAL Problem with "Enable layer select mode" option.
2869122 CONCEPT_HDL OTHER Infinite loop: "WARNING(SPCOCN-1522): Cannot create note without text" when starting note with a double quote (")
2864910 CONSTRAINT_MGR SYSCAP NetClass shows stale members when using SKILL API to query members
2874741 CONSTRAINT_MGR SYSCAP After commit, it asks to save the project at the time of closing the project
2890763 CONSTRAINT_MGR TOPOLOGY Reference layers missing from reference layers Table in exported TOP file
2762447 PCB_LIBRARIAN SYMBOL_EDITOR Cant change documentation grid in NSE
2820516 PCB_LIBRARIAN SYMBOL_EDITOR Documentation grid is incorrect in NSE
2191276 PSPICE SIMULATOR Inconsistent bias point results with Vpulse source.
2243592 PSPICE SIMULATOR Long .param statement in .include file NOT included, with no warning or error.
2362386 PSPICE SIMULATOR Modify bias point file is unable when a encrypted model is placed on circuit
2704970 PSPICE SIMULATOR Incorrect bias point when VOFF is defined in curly braces for AC analysis
2881948 PSPICE SIMULATOR Return Value of PSpiceCommandDo
470277 PSPICE SIMULATOR Node limitation for poly devices
2879621 PULSE DASHBOARD Project Dashboard and the Open Projects takes longer time than expected in SPB 22.1
2649617 PULSE LIVEBOM Need option to expand Mechanical Kits in Live BOM
2794509 PULSE LIVEBOM Unable to add a mechanical part to the selected variant Live BOM in System Capture.
2796426 PULSE LIVEBOM Mechanical Kit added to Live BOM does not get expanded into its separate mechanical parts.
2827549 PULSE LIVEBOM Live BOM in collapsed mode displays properties not present on parts as associated properties.
2766613 PULSE R2PLM-3DX When the first document in the Publish to PLM using PFM fails, all documents fail to publish
2801217 PULSE R2PLM-LIBSYNC Error while Configuring the New Part Request
2844225 PULSE R2PLM-TC Need ability to add mechanical parts without part reference in PFM output for PLM system BOM
2787526 PULSE R2PLM Want to set up rules that runs together in PfM under Mandatory Utilities Settings.
2871488 SYSTEM_CAPTURE ADHOC Update runs but never completes on a project
2701676 SYSTEM_CAPTURE BOM Syscap variant bom_ignore variable request to be more versatile
2758195 SYSTEM_CAPTURE BOM Allow ability to set value of BOM_IGNORE property to something other than TRUE or FALSE
2759480 SYSTEM_CAPTURE BOM Need the ability to put in any value for the BOM_IGNORE property in System Capture.
2804432 SYSTEM_CAPTURE BOM Need the ability to put in any value for the BOM_IGNORE property in System Capture
2845538 SYSTEM_CAPTURE COMPOSITE_FIL Project creation using Tcl fails when the folder name has specific extension in its name
2881631 SYSTEM_CAPTURE CONSTRAINT_MA Netslass members added to other net classes after importing sheets from System Capture
2874375 SYSTEM_CAPTURE CRASHLOGGER Crash logger enhancement request to log more information
2622968 SYSTEM_CAPTURE CROSSPROBE Cross-probing from Allegro to System Capture does not open the schematic sheet
2849490 SYSTEM_CAPTURE CROSSPROBE Cross probing from PCB Allegro doesn't open the corresponding Schematic sheet
2851928 SYSTEM_CAPTURE CROSSPROBE Cross-probing from PCB Editor should open the schematic sheet in System Capture on which the component exists.
2862054 SYSTEM_CAPTURE CROSSPROBE Cross probing from PCB Editor should open the corresponding schematic sheet
2883612 SYSTEM_CAPTURE DBDOCTOR System Capture performance degrades after running DBDoctor
2230443 SYSTEM_CAPTURE DELETE Option to have Delete Multiple Pages feature similar to Insert Multiple Pages
2345298 SYSTEM_CAPTURE DELETE Enhancement request to allow for the deletion of multiple pages rather than 1 page at a time. Functionality exists in DE
2479274 SYSTEM_CAPTURE DELETE In System Capture cannot delete multiple pages
2748050 SYSTEM_CAPTURE DELETE Delete multiple pages in System Capture design.
2847001 SYSTEM_CAPTURE EXPORT_PCB Room not created when set on hierarchical blocks in the design
2867920 SYSTEM_CAPTURE FIND_REPLACE Pasting a string from a CSV or XLSX file appends a space to the end of the pasted string
2884645 SYSTEM_CAPTURE IMPORT_BLOCK CPLIB-2 error reported when 2 or more design imports are done during the same Syscap session
2869315 SYSTEM_CAPTURE MENUS_AND_TOO New Symbol Editor toolbar should be moved to the top edge of the interface
2892599 SYSTEM_CAPTURE MENUS_AND_TOO Toolbar icons remain highlighted (blue) after command is completed
2834077 SYSTEM_CAPTURE MISCELLANEOUS In 22.1 ISR4 Help ->Documentation is not working
2867334 SYSTEM_CAPTURE NAVLINKS TCL-Command navlinks -gen/-off does not change state of View > Navigation links
2798993 SYSTEM_CAPTURE PAGE_BORDER Unable to hide/unhide and add/remove properties attached to format or Page Border in System Capture.
2903114 SYSTEM_CAPTURE PART_MANAGER Design update to latest version fails and changed pages get removed.
2845023 SYSTEM_CAPTURE PRINT Printed text size is inconsistent when dealing with blocks
2867222 SYSTEM_CAPTURE PRINT Print pdf in System Capture takes a 6 min on a large design
2864163 SYSTEM_CAPTURE REPLACE Replace split part does not preserve the reference designator
2884541 SYSTEM_CAPTURE REPLACE Refdes is not preserving when changing the symbol version
2891962 SYSTEM_CAPTURE REPLACE Component Find and Replace creates disconnected pins/wires
2904296 SYSTEM_CAPTURE REPLACE Component replace changing reference designator.
2889737 SYSTEM_CAPTURE SCRIPTING clearViolationMessage is not working for user violation messages
2869144 SYSTEM_CAPTURE SHORTCUTS Syscap crashes at the time of launch with tcl file placed at site
2878390 SYSTEM_CAPTURE SMART_PDF Text issues when printing using smart PDF in System Capture.
2877812 SYSTEM_CAPTURE SPECIAL_SYMBO Bug with vcc_bar and v_bar symbols
2860187 SYSTEM_CAPTURE TABLE Import CSV file fails to bring the CSV contents if the design name has a hyphen or folder name has space
2859408 SYSTEM_CAPTURE TABLE_OF_CONT Syscap crashes when running Configure Schematic audit settings for multiple projects and on multiple machines
2880728 SYSTEM_CAPTURE UI System Capture hangs when user tries to select and move circuit or multiple wires
2908467 SYSTEM_CAPTURE UI topwb crash when using "make same size"
2841501 SYSTEM_CAPTURE UNIFIED_SEARC Filters loading in Unified Search takes 10 seconds for 28k parts
2850280 SYSTEM_CAPTURE UNIFIED_SEARC Scroll bar not coming or not scrolling till the end for classification filter
2855864 SYSTEM_CAPTURE UNIFIED_SEARC Syscap does not allow to make column visible in Unified search window
2879942 SYSTEM_CAPTURE UNIFIED_SEARC Unified Search Filter Panes
2883802 SYSTEM_CAPTURE UNIFIED_SEARC Getting SPPSUN-5 error while adding property header to Unified search.
2884771 SYSTEM_CAPTURE UNIFIED_SEARC Unified Search Filter display issue
2785940 SYSTEM_CAPTURE VARIANT_MANAG symbol is not having pin numbers in variant view
2872114 SYSTEM_CAPTURE VARIANT_MANAG Enable directive to skip jedec compatibility checks in Alt parts for variant flow in System Capture
2880027 SYSTEM_CAPTURE VARIANT_MANAG Disabling Show Cross on DNI does not work
2886288 SYSTEM_CAPTURE VERSION_WIDGE System Capture exits on selecting a part in attached design
2875747 SYSTEM_CAPTURE WIRING Adding inport to wire gives error: This operation leads to invalid connectivity.
2880370 SYSTEM_CAPTURE WIRING Moving wires created an extra wire
2890679 SYS_RELIABILITY AUDIT_RULES Running ERC takes too long on a customer design
2892258 SYS_RELIABILITY AUDIT_RULES Schematic Audit ERROR(SYSR-46) error occurred while running graphical audit rules.
2892814 SYS_RELIABILITY AUDIT_RULES Design Integrity Audit checks gives ERROR SYSR-46
2867396 TOPXP OPTIMALITY_IN TOPXP-optimality Parallel Bus Bad eye diagrams are ignored when using BER eye height as objective function
2897054 TOPXP SSIVIEWER The min Jitter margin is shown as a negative value.
2752709 TOPXP SWEEP_MANAGER NMP(no measurement possible) in LPDDR5 report
2852801 TOPXP SWEEP_MANAGER Standby IO Model parameters are missing in sweep manager with SPB22.1 S005 build
2890620 TOPXP SYSTEMSI TdlVW/VdlVW values of DDR4-2400 differ with JEDEC’s Specifications
2898169 TOPXP SYSTEMSI Question about stimulus definition in Micron y32a.ibs on set to the controller block





Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence SPB Allegro and OrCAD
Version: 2023
Supported Architectures: x64
Website Home Page : www.cadence.com
Languages Supported: english
System Requirements: Windows *
Size: 15.3 Gb


** included:

Base_SPB17.40.000_wint
Hotfix_SPB17.40.033_wint

** System Requirements:

System Requirements:

OS: Windows 10 (64-bit) Professional, Windows Server 2012 (All Service Packs); Windows Server 2012 R2; Windows Server 2016.
CPU: Intel Core i7 4.30 GHz or AMD Ryzen 7 4.30 GHz with at least 4 cores
Memory: 16 GB RAM
Space: 50 GB free disk space (SSD drive is recommended)
Display: 1920 x 1200 display resolution with true color (at least 32bit color)
GPU: A dedicated graphics card supporting OpenGL, minimum 2GB (with additional support for DX11 for 3D Canvas)
Monitors: Dual monitors (For physical design)
Supported MATLAB Version: R2019A-64Bit (For the PSpice-MATLAB interface)
本部分内容设定了隐藏,需要回复后才能看到


关于激活
完整图文激活教程:https://www.sdbeta.com/wg/2019/1021/231934.html
- Remove old versions

- Install "Cadence License Manager 12.08S" SPB17.40.000.Full.Setup.DVD1\Disk1\LM and close "Cadence License Server Configuration" window

- Select "Product Installation" and install app with default settings

- Copy and replce "LicenseManager" folder to "C:\Cadence\" and run "LicenseManagerPubKey.bat"

- Copy and replce "tools" to "C:\Cadence\SPB_17.4\" and run "ToolsPubKey.bat" Wait...!

- Copy "License.dat" to "C:\Cadence\LicenseManager"

- In "C:\Cadence\LicenseManager\" open "LicenseServerConfiguration.exe" and point "License.dat" (Click Next and Finish)

- In "C:\Cadence\LicenseManager" open "license.dat" with editor and REMOVE ONLY tow line after "DAEMON cdslmd"
SERVER localhost ID = 07071982 5280
DAEMON cdslmd
"C:\Cadence\SPB_17.2\LicenseManager\cdslmd
.exe" PORT=3000

Will be:

SERVER localhost ID = 07071982 5280
DAEMON cdslmd

- In "C:\Cadence\LicenseManager" open "lmtools.exe", select "Start/Stop/Reread" Tab and click on "Stop Server" then "Start Server"

few notes by:WhiteDeath
The license.dat will work perfect on 90% of the applications/tools sadlly cauze this new Cadence SPB Allegro and OrCAD v17.40 2 or 3 tools maybe need new license.dat fixed.
i manage fix some edit the license.dat but only for all tools that are 17.4 and most of the utilities...
2) both iso's required in when start main installation will request the disk\data3.cab
option 1: mount the SPB17.40.000.Full.Setup.DVD1 install license manager and then start the main installation when ask for date3.cab just unmount and mount the DVD2
option 2: just extract all files / folder in one folder on your desktop and follow the same without need mount etc....




















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离线xcgd520

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只看该作者 沙发  发表于: 2019-10-21 21:06:33
支持一下,感谢分享
离线raytheon

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只看该作者 板凳  发表于: 2019-10-22 23:44:17
cadence 很强大的设计工具
离线空古悠岚

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只看该作者 地板  发表于: 2019-10-23 21:43:00
现在估计用16.6的还有不少
离线louiszhu

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只看该作者 地下室  发表于: 2019-10-25 12:41:09
谢谢分享 下载学习
离线ccckxxx

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只看该作者 5 发表于: 2019-10-26 21:23:40
电路板设计软件,谢谢分享
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离线030711

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只看该作者 6 发表于: 2019-11-23 08:24:02
Cadence SPB Allegro and OrCAD 17.40.001-2019 破解版
离线030711

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只看该作者 7 发表于: 2019-11-23 09:13:20
Cadence SPB Allegro and OrCAD v17.40.001-2019 Hotfix Only x64
离线z9919195

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只看该作者 8 发表于: 2019-12-11 13:01:57
目前还只是在用16.6
离线takaya

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只看该作者 9 发表于: 2019-12-11 13:07:36
感谢感谢。