Mentor Questa Formal 2021.1 | 1.4 Gb
Mentor Graphics Corporation, a Siemens business, is pleased to announce the availability of Questa Formal 2021.1. This solution find obscure bugs, increasing design confidence through exhaustive analysis, before simulation test environments are available, and also boost productivity and functional verification quality by targeting verification tasks that are difficult to complete. 2021.1 Release Notes Major New Features in 2021.1Version 2021.x releases have significant enhancements and changes compared with the 2020.x series of releases.New Tcl Commands- cdc promote constraint - new directive to change the promotion attributes of specified CDC constraint.- resetcheck preference isolation - new directive to set preferences for isolation strategies.New Reset Check Schemes/Checks- reset_as_data - asynchronous set or reset signal is connected to data pin.New Lint Checks- case_small - case statement has fewer case items.- comment_density_low - comment density of a design file is less than the specified limit.- func_arg_array_constrained - function argument is a constrained array.- module_has_multi_clks - multiple sequential blocks use the same clock.- net_decl_with_assign - net is declared and assigned in the same statement- package_disallowed - use of the specified package is not allowed.- package_name_not_standard - package name does not follow standard naming rules.- pragma_disallowed - use of the specified pragma is not allowed.- reg_reset_value_disallowed - register is assigned a reset value, which is not allowed.- sync_control_is_internal - synchronous control signal is internally generated. The following table list the customer defects fixed and enhancements requested in the 2021.1 release. Enhancements in v2021.1 CDC-27785 CDC-28311 Added a new reset tree check, reset_as_data, which checks if a set or reset signal is connected to the data pin.
CDC-27890 Enhanced the CDC tool to report warning, directive-558, for non-support of SDC directive set_clock_groups -logically_exclusive.
CDC-28479 Added support for Microsemi Libero 12.4 RTG4 library.
CDC-28588 Enhanced the RDC GUI and added options to filter check violations based on instance.
CDC-28795 Enhanced license management for Signoff CDC tool.
CDC-28830 Enhanced CDC by reducing processing time while elaborating a design with IP-XACT register arrays.
CDC-28965 Added support for the DW_ecc DesignWare component.
CDC-28988 Enhanced CDC by introducing sdc preference-logically_physically_exclusive option to consider the set_clock_sense -logically_exclusive and -physically_exclusive options for CDC analysis.
CDC-29064 Enhanced the sdcAllowRegNamingStyle tcl variable to differentiate between ports and registers when design is loaded.
FORMAL-20489 Enhanced Formal tools by suppressing the warning flagged while running AutoCheck GUI from Vivado.
FORMAL-20558 Enhanced the formal-337 warning to provide the information about DB version, which helps isolate the cause of the problem.
LINT-6407 Added the signal_name_not_standard check to the STARC-based goal.
LINT-6415 Added package_disallowed check to the STARC-based goal.
LINT-6621 Introduced sync_control_is_internal check to flag warnings for instances where synchronous control is internally generated.
LINT-6622 Introduced comment_density_low check to flag instances where comment density of a file is less than the specified limit.
LINT-6971 Enhanced the process_has_inconsistent_async_control check by adding a new directive option -include_vh_variable_flops to flag check violations for VHDL variables that might get synthesized into flops.
LINT-7021 Introduced case_small check to flag warning for instances where case statement has fewer case items than the specified limit.
LINT-7081 Enhanced the data_type_not_recommended check by adding a new directive option -apply_to_vhdl_constructs to flag check violations for specific VHDL constructs.
LINT-7171 Enhanced the reserved_keyword check by adding a new directive option -reserve_user_words_file to specify a file with the list of user-defined keywords. The check flags violations when any of these keywords is found in the design.
LINT-7363 Enhanced the var_read_before_set check to:
- detect read expressions within initialization assignments for
variables declared inside Verilog 'always' blocks.
- detect read expressions within array indices in Verilog and VHDL.
LINT-7389 Enhanced the process of Lint migration from an older version to a more recent version.
VISU-21081 Enhanced the Lint Checks window to display the total and selected number of violations.
Bug Fixes in v2021.1 CDC-9234 Fixed the issue that led to large memory consumption during the synthesis of huge case statements.
CDC-27268 CDC-28374 Fixed the issue that generated false multi-clock reconvergence instances without enabling the cdc preference reconvergence-multi_clock_convergence directive.
CDC-27829 Fixed an issue with elaboration during CDC analysis.
CDC-28467 Fixed an issue with the propagate_clks_for_ram process.
CDC-28476 Fixed an RDC issue of reporting false dual polarity paths through tristate.
CDC-28520 Fixed a memory consumption issue that was encountered during a design analysis.
CDC-28678 Added the support for altera_syn_attributes package.
CDC-28699 Fixed an issue to correct the inference of rx_data port in the FX checker.
CDC-28989 Fixed the issue where a Fatal error was reported when a VHDL design had width mismatch.
CDC-29009 Fixed an issue with the handshake scheme.
CDC-29012 Fixed an issue with the HDM top-down CDC analysis.
CDC-29026 Fixed the CDC issue where the tool missed reporting a no_sync crossing.
CDC-29028 Added missing parameters in the Microsemi polarfire library models.
CDC-29062 Fixed the RDC issue where stable signal was not propagated through a MUX and led to reporting of false RDC violations.
CDC-29196 Fixed the issue that reported liberty messages during elaboration and netlist create phases. The messages are now suppressed.
CDC-29197 Fixed the issue where a while loop in a VHDL design caused a module to be black-boxed.
CDC-29206 Fixed the issue that generated a false parser-296 warning.
CDC-29207 Fixed an issue with get_cells and get_clocks which returned a non-empty collection for unmatched cells/clocks.
CDC-29225 Fixed the issue that did not consider the following clocks while resolving clock groups, although inferred them as clocks:
- generated clock or master clock
- related_pin of a pin with falling_edge/rising_edge timing_type
CDC-29238 Fixed the cdc_mfx checker issue where the clocks_aligned signal that remained as X at all times, drove the RX signal to X.
CDC-29239 Fixed the issue that led to an unintended tool behavior during library implementation.
CDC-29307 Fixed an issue where get_pins did not match the pins of cells that were marked as black-box.
CDC-29377 Fixed the issue that did not infer clock relationship between two internal pins associated with one another. The tool created a new group instead of associating them with the parent group.
FORMAL-19697 Fixed the issue that generated a command failure message when grid submit command starts with a white space.
FORMAL-19781 Fixed the issue that generated an unexpected signal error while running CoverCheck compiler.
FORMAL-20082 Enhanced the Formal tool behavior to treat the port as actual which is used for the instantiation, if a port from a configuration cannot be found in the component port list.
FORMAL-20248 Fixed the issue that generated the error: “Too many ports specified for instance” while instantiating a module.
FORMAL-20255 Fixed the issue in ConnectCheck that generated a fatal error while enabling coverage on a design with SVI.
FORMAL-20529 Removed the support for the -init option from the *verify commands. To manually specify an initialization sequence to the tool, use the formal init directive instead.
FORMAL-20577 Fixed the issue that generated an error while running the AutoCheck generated shell script from Vivado.
FORMAL-20627 Fixed the issue due to which amessage was neither reported in the Message Viewer in the PropCheck GUI nor it was reported in the formal_verify.log file.
FORMAL-20676 Fixed the issue due to which ConnectCheck parser generated wrong line number for a checker name.
FORMAL-20760 Fixed the issue that led to an incorrect FSM visualization in the PropCheck tool.
FORMAL-20761 Fixed the issue in AutoCheck that generated an unexpected elaboration-523 error.
FORMAL-20794 Fixed the memory issue encountered while running qverify_capture to generate the setup for recompile in AutoCheck.
FORMAL-20800 Fixed the issue due to which a false error “vopt-2734: Failed to find <module> in hierarchical name” is generated.
FORMAL-20913 Fixed an issue with the formal compile command.
FORMAL-20930 Fixed the compile time issue that increased after some HDL updates were done on a design.
FORMAL-20937 Fixed the issue which generated inconsistent results when a module interface uses real types or unused real types.
FORMAL-20938 Fixed the issue due to which a design could not be elaborated or synthesized for Connectivity Explorer or Lint.
FORMAL-20992 Fixed the issue with the directive option netlist reset -remove.
FORMAL-21005 Fixed the issue that generated an error while generating UCDB when compile step is performed in one directory and verify step is performed in another.
FORMAL-21007 Added a new message to warn user that formal code coverage data is not saved when the UCDB is generated with only one reachability or observability.
FORMAL-21012 Fixed the issue where inconsistent results were displayed in the Design tab of the GUI.
FORMAL-21058 Fixed the issue that caused inconsistencies in the reports when generated with -detail and -detail_all option of the formal generate coverage command.
FORMAL-21113 Fixed an elaboration issue with ConnectCheck.
LINT-671 Enhanced the multi_driven_signal check to report the line number of the location where the signal is driven instead of reporting the line number of the declaration. To switch to reporting on declaration line, use debug flag lint_backward_compatible_2020_4.
LINT-5943 Replaced the check func_input_array_constrained with func_arg_array_constrained check. func_arg_array_constrained supports directive lint preference -port_mode to flag violations for specific port modes.
LINT-7176 Fixed an issue with the lint preference name directive.
LINT-7527 Fixed an issue with var_read_before_set check which flagged false violations when a variable was initiated in the first 'if' branches. After the fix, the check does not flag a variable which is read in the first ‘if’ branch when that branch checks for an enclosing loop variable being equal to its initial value.
VISU-22968 Fixed an issue that led to the display of non-existent violations in the RTL source window of the Questa Lint tool.
VISU-23100 Fixed the CDC/RDC filter dialog box and added the missing Create Directive button.
The Questa verification solution from Siemens EDA, a part of Siemens Digital Industries Software, continues to evolve in response to the growing complexity of SoC designs. Besides the sheer size of designs, the inclusion of multiple embedded processors and advanced interconnect systems, increasing software content and the configurability required by multi-platform based designs require a functional verification solution that unifies a broad arsenal of verification solutions. Questa lets you apply CDC verification, formal verification, mixed-signal verification, portable stimulus, and other powerful technologies to maximize the effectiveness of your verification at the block- and subsystem-level so your system-level verification can focus on system-level functionality, including software, without having to worry about lower-level bugs taking away from your productivity. No one wants to compromise product quality. However, time-to market pressures dominate SoC projects. To deliver quality within schedule requires improving the time to achieve coverage and quality goals and improving debug productivity. Questa Formal Apps statically analyze a design’s behavior with respect to a given set of properties; then exhaustively explore all possible input sequences in a breadth-first search manner. This uncovers design errors that would otherwise be missed or are impractical to find with simulation-based methods. Questa Formal Apps boost verification efficiency and design quality by exhaustively addressing verification tasks that are difficult to complete with traditional methods, and they don’t require formal or assertion-based verification experience. Properties are synthesized from a combination of automatic RTL design analysis and a high-level specification of design intent. The generated properties are then exhaustively verified with formal analysis engines. The Questa Formal App suite includes applications to address tasks such as: static and conditional connectivity checking, secure path integrity checking, unreachable code identification, X-state propagation, state-space analysis, and register verification. Additionally, the Questa Sequential Logic Equivalence Checking (SLEC) App uses formal methods to perform exhaustive comparisons between inputs to reveal any behavioral discrepancies that could arise in clock gating, ECO integration, re-pipelining, or fault mitigation logic. Questa Verification Management Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world’s most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Product: Mentor Questa FormalVersion: 2021.1Supported Architectures: x64Website Home Page : https://eda.sw.siemens.com/Languages Supported: englishSystem Requirements: PC *Size: 1.4 Gb * System Requirements:
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