[行业软件]Cadence OrCAD X Platform 2023 (23.10.002) [复制链接]

Cadence Design Systems, Inc. has released Cadence OrCAD X Platform 2023 (23.10.002) Hotfix is cloud-enabled system design solution that offers transformative improvements in ease of use, performance, automation and collaboration.



Fixed CCRs: SPB 23.1 HF002 - Date: 02-09-2024


2719952 ALLEGRO_EDITOR 3D_CANVAS Symbol Pin - Plating Issue on 2Layer designs
2735717 ALLEGRO_EDITOR 3D_CANVAS Get error "Bend operation are disabled because bend engine has encountered an error" when opening 3D Canvas
2802922 ALLEGRO_EDITOR 3D_CANVAS Lines on SURFACE FINISHES / CARBON_BOTTOM not displayed in 3D Canvas
2862872 ALLEGRO_EDITOR 3D_CANVAS 3D Mapper rendering issue
2877216 ALLEGRO_EDITOR 3D_CANVAS (SID: 54647) Shape on BOARD GEOMETRY - SILKSCREEN_TOP displayed on 3D Canvas incorrectly?
2890683 ALLEGRO_EDITOR 3D_CANVAS Allegro Crash when user click on "OK" or "Apply" in Preference window in 3D Canvas
2780459 ALLEGRO_EDITOR DATABASE Pad of bottom side SMD on via does not get mapped to bottom surface layer of zone
2879973 ALLEGRO_EDITOR DATABASE DBDoctor WARNING(SPMHA1-97): Illegal drill plating reported for SMD pins with no drill
2884980 ALLEGRO_EDITOR DATABASE Unable to open board created in 17.4 and tool getting crashed
2811667 ALLEGRO_EDITOR DFA DFA Table in CM does not accept 1.0x values
1566989 ALLEGRO_EDITOR DFM Add DRC check for actual drill bit size for plated hole/slot padstacks
2058669 ALLEGRO_EDITOR DFM Constraints Spacing Hole to, to show DHS instead of FHS
2259992 ALLEGRO_EDITOR DFM Allow drill to metal DRC check to use Drill tool size specified in the padstack editor instead of FHS drill size
2517674 ALLEGRO_EDITOR DFM Align drill tool size with database units and accuracy
2779490 ALLEGRO_EDITOR DFM Enhance Drill chart table to suppress display of finished hole size when drill tool size is present
2853309 ALLEGRO_EDITOR DFM DFF Minimum Shape Width (positive) not flagging violations for shape widths smaller than rule
2878246 ALLEGRO_EDITOR DFM Design have alot of fasle uvia hole 2 uvia hole same net DRC
2814824 ALLEGRO_EDITOR DRC_CONSTR Waived InterLayer Check DRC
2890201 ALLEGRO_EDITOR DRC_CONSTR Ability to override min void spacing return path DRCs for clines coming out of pin/via tied to same net as cline
2882540 ALLEGRO_EDITOR DXF DXF export functoin changes after SPB17.4_S026
2866590 ALLEGRO_EDITOR EDIT_ETCH Cannot cancel command on locked via slide.
2581238 ALLEGRO_EDITOR GRAPHICS new gpu mode and right click (hold down) mouse always end up in stroke mode
2894603 ALLEGRO_EDITOR GRAPHICS Color assignment to bundles not working properly
2907715 ALLEGRO_EDITOR GRAPHICS You have to do a manual refresh after using the delete by delete by rectangle
2907764 ALLEGRO_EDITOR GRAPHICS Program Crash in GPU mode
2920709 ALLEGRO_EDITOR GRAPHICS Performance of SKILL script is affected by having GPU acceleration turned on
2893142 ALLEGRO_EDITOR OTHER Teardrops will sometimes disappear
2888541 ALLEGRO_EDITOR PLOTTING Plotting is not working as expected in Allegro PCB Editor 23.1 P001
2907559 ALLEGRO_EDITOR PLOTTING Plot scaling options generates similar output irrespective of the option selected
2921958 ALLEGRO_EDITOR PLOTTING Issues with axlcanvasprinttoPDF API
2862778 ALLEGRO_EDITOR PULSE Failing to migrate a DE_HDL/MMD based design into a Pulse managed MDD based board
2858155 ALLEGRO_EDITOR SCHEM_FTB Netlist import fails with error in changes only mode
2805010 ALLEGRO_EDITOR SHAPE Slide of arc segment for a shape uses last pick and not arc/circle center to use ix/iy easily
2897491 ALLEGRO_EDITOR SHAPE Updating shape of Cross hatch to smooth is using very long time when Fill Xhatch cells is in "LOW" state
2866219 ALLEGRO_EDITOR SKILL axlPurge3DModelMapDataInDesign skill function does not exist
2909896 ALLEGRO_EDITOR SRM SRM: Enhance SRM to Download Symbols in a group of N, Where N should be configurable
2879140 ALLEGRO_EDITOR UI_FORMS form_user_size env variable impact UI of Allegro Menus
2902524 ALLEGRO_EDITOR UI_FORMS SKILL assignment of #RGB color code produces crash when testing axlform.il graphics
2865591 ALLEGRO_EDITOR UI_GENERAL axlDMDirectoryBrowse - "Directory:" field prefilled and "Choose" button disabled
2735159 ALLEGRO_EDITOR ZONES Unable to map zones containg via structures
2810515 ALLEGRO_EDITOR ZONES Rigid Flex design Zone Layer stackup change - best process/methodology
2882923 ALLEGRO_EDITOR ZONES PCB Editor abruptly closes after DRC update
2893834 ALLEGRO_EDITOR ZONES Allegro PCB is crashing often randomly for unclear reasons and now the dbdoctor is crashing on brd file
2873324 APD DATABASE Length constraint value display truncated to max integer
2877122 APD DATABASE Total etch length limit is giving weird results when show element
2876619 APD DEGASSING Metal usage report is causing APD to crash
2881864 APD DEGASSING DXF export fails with "dxf_out exportlinesasshapes YES"
2902562 APD DEGASSING Issues with gerber file generation
179822 APD DRC_CONSTRAIN Enhancement for custom Constraints between Padstacks
1990562 APD DRC_CONSTRAIN Additional parameter in padstack editor to differentiate via options
2591954 APD DRC_CONSTRAIN The new rules item for checking among BBvia structures in the same net spacing
2801475 APD DRC_CONSTRAIN Enhance ConsManager to support via classes defined by padstack type with different constraint values between classes
575104 APD DRC_CONSTRAIN Allegro can set spacing from differentiate test vias to other elements.
2863469 APD EDIT_ETCH Very slow performance of sliding a trace and delay tune (No shapes)
2881863 APD OTHER Layer Compare Batch fails if ifllets are present
2865593 APD SHAPE Adding fillet to uVia doubles the uVia-to-shape SN spacing
2882751 APD SHAPE When running Update Shape, the dynamic shape is voided with incorrect clearance
2866861 APD UI_GENERAL Problem with "Enable layer select mode" option.
2890478 APD WLP Import Techfile : Pad shape size needs to be translated with new behavior
2891217 APD WLP Import Techfile : Replace BELOW and ABOVE by vias for refVia attribute
2891782 APD WLP Shape Width Auto Fixer: Create keepout shapes by using PVS marker directly
2893736 APD WLP Pin extensions should be updated when symbol is moved
2896424 APD WLP silicon layout option create package edge connector will not work on module with floating clines that cross boundary
2898336 APD WLP Import Techfile : Incorrect Line-VIA spacing in CoWoS-R testcase (L-V should be 2UM, not 3UM)
2899583 APD WLP PM-over-UBM Special Density auto fixer can't process on DRM_048 based design
2905345 APD WLP Package Integrity Check for Techfile: Incorrect Turn Angle Value
2910284 APD WLP Keepout DRC does not work after setting spacing tolerance
2873140 CAPTURE NETLIST_ALLEG Component mismatch on crossprobing when using query in PCB with multiple pages open in capture
2869122 CONCEPT_HDL OTHER Infinite loop: "WARNING(SPCOCN-1522): Cannot create note without text" when starting note with a double quote (")
2874741 CONSTRAINT_MGR SYSCAP After commit, it asks to save the project at the time of closing the project
2890763 CONSTRAINT_MGR TOPOLOGY Reference layers missing from reference layers Table in exported TOP file
2883074 CONSTRAINT_MGR UI_FORMS Copy paste on reference layer in CM doesn’t copy table information
2890153 CONSTRAINT_MGR UI_FORMS Ability to copy reference layers table from cell to cell in return path worksheet in CM
2899068 PCB_LIBRARIAN LIBDB_GRAPHIC "BPC23_LIB" Quit unexpectedly diagnostic data in sprint1
2901846 PCB_LIBRARIAN LIBDB_GRAPHIC "BPC23_LIB" Quit unexpectedly diagnostic data in sprint1
2362386 PSPICE SIMULATOR Modify bias point file is unable when a encrypted model is placed on circuit
2881948 PSPICE SIMULATOR Return Value of PSpiceCommandDo
2898391 PSPICE SIMULATOR PSpice will crash with some sub-circuit model.
2774130 PSPICE TI_CONTRACT GUI options to retain the comment lines for encrypted library
2900272 PULSE ADHOC Board file opened from Pulse gets downloaded to incorrect location
2686636 PULSE CORE Support cloud application proxy for ODM collaboration
2913739 PULSE CORE Multiple app instances cause many app proxy login requests
2766613 PULSE R2PLM-3DX When the first document in the Publish to PLM using PFM fails, all documents fail to publish
2787526 PULSE R2PLM Want to set up rules that runs together in PfM under Mandatory Utilities Settings.
2871581 RF_PCB BACK_ANNOTATI Pin Pair Errors during export to layout even if the schematic did not change
2885836 RF_PCB BACK_ANNOTATI XNETS issue when backannotation is performed
2871488 SYSTEM_CAPTURE ADHOC Update runs but never completes on a project
2881056 SYSTEM_CAPTURE BOM BOM HDL failed to launch on user's machine
2911991 SYSTEM_CAPTURE BYPASSRAIL System Capture Replace in Find/Replace and Part Manager only replaces first cap in bypass rail
2771077 SYSTEM_CAPTURE CONSTRAINT_MA With Read-Only design opened in System Capture, allow the launch of Read-Only Constraint Manager
2810286 SYSTEM_CAPTURE CONSTRAINT_MA Constraints flowing from System Capture to Allegro
2864079 SYSTEM_CAPTURE CONSTRAINT_MA Disable Constraint Editing in System Capture
2881631 SYSTEM_CAPTURE CONSTRAINT_MA Netslass members added to other net classes after importing sheets from System Capture
2885992 SYSTEM_CAPTURE CONSTRAINT_MA Not able to "view" constraints (e.g. during a design review) if the schematic is locked by a user
2622968 SYSTEM_CAPTURE CROSSPROBE Cross-probing from Allegro to System Capture does not open the schematic sheet
2849490 SYSTEM_CAPTURE CROSSPROBE Cross probing from PCB Allegro doesn't open the corresponding Schematic sheet
2851928 SYSTEM_CAPTURE CROSSPROBE Cross-probing from PCB Editor should open the schematic sheet in System Capture on which the component exists.
2859741 SYSTEM_CAPTURE CROSSPROBE Lag during cross probe from schematic to PCB, and SysCap screen blackens out while cross probing from PCB.
2862054 SYSTEM_CAPTURE CROSSPROBE Cross probing from PCB Editor should open the corresponding schematic sheet
2917993 SYSTEM_CAPTURE CROSSPROBE Cross Probe performance between Allegro and System Capture is very slow
2883612 SYSTEM_CAPTURE DBDOCTOR System Capture performance degrades after running DBDoctor
2230443 SYSTEM_CAPTURE DELETE Option to have Delete Multiple Pages feature similar to Insert Multiple Pages
2345298 SYSTEM_CAPTURE DELETE Enhancement request to allow for the deletion of multiple pages rather than 1 page at a time. Functionality exists in DE
2479274 SYSTEM_CAPTURE DELETE In System Capture cannot delete multiple pages
2748050 SYSTEM_CAPTURE DELETE Delete multiple pages in System Capture design.
2888366 SYSTEM_CAPTURE FORMAT_OBJECT Refdes Font color cannot be changed
2900210 SYSTEM_CAPTURE IMPORT_BLOCK CGCAN-322: Page border not found with New Project From Existing Design (DEHDL)
2881016 SYSTEM_CAPTURE IMPORT_PCB For Chinese OS, wrong characters displayed in session log window
2898640 SYSTEM_CAPTURE IMPORT_PCB Unable to back-annotate pin swaps using Import PCB Layout
2869315 SYSTEM_CAPTURE MENUS_AND_TOO New Symbol Editor toolbar should be moved to the top edge of the interface
2892599 SYSTEM_CAPTURE MENUS_AND_TOO Toolbar icons remain highlighted (blue) after command is completed
2834077 SYSTEM_CAPTURE MISCELLANEOUS In 22.1 ISR4 Help ->Documentation is not working
2880026 SYSTEM_CAPTURE MISCELLANEOUS System Capture crash during a commit
2885798 SYSTEM_CAPTURE PACKAGER PB NETREV Components unplaced into the board after import netlist even if all needed properties like JEDEC_TYPE are pres
2898663 SYSTEM_CAPTURE PART_MANAGER Part manager changes property location/justification
2903114 SYSTEM_CAPTURE PART_MANAGER Design update to latest version fails and changed pages get removed.
2844113 SYSTEM_CAPTURE PRINT Printed schematic may not match displayed Canvas or appear truncated
2845023 SYSTEM_CAPTURE PRINT Printed text size is inconsistent when dealing with blocks
2867222 SYSTEM_CAPTURE PRINT Print pdf in System Capture takes a 6 min on a large design
2884541 SYSTEM_CAPTURE REPLACE Refdes is not preserving when changing the symbol version
2891962 SYSTEM_CAPTURE REPLACE Component Find and Replace creates disconnected pins/wires
2904296 SYSTEM_CAPTURE REPLACE Component replace changing reference designator.
2889737 SYSTEM_CAPTURE SCRIPTING clearViolationMessage is not working for user violation messages
2898664 SYSTEM_CAPTURE SCRIPTING Design crashes when extracting meta data
2905685 SYSTEM_CAPTURE SHORTCUTS Atl+Key is working only for "Above" command, Alt+key should not work for any command.
2878390 SYSTEM_CAPTURE SMART_PDF Text issues when printing using smart PDF in System Capture.
2888720 SYSTEM_CAPTURE SMART_PDF Smart PDF creation for System Capture variant inherits wrong part attributes
2860900 SYSTEM_CAPTURE SYMBOL_CREATO Note justification not working when placing a note in block symbol editing mode.
2859294 SYSTEM_CAPTURE SYMBOL_GRAPHI Arcs cannot be resized, snap back to initial location.
2859408 SYSTEM_CAPTURE TABLE_OF_CONT Syscap crashes when running Configure Schematic audit settings for multiple projects and on multiple machines
2905735 SYSTEM_CAPTURE TABLE_OF_CONT Making a placed table larger (have more columns and rows) is broken on TOC page
2910042 SYSTEM_CAPTURE TABLE_OF_CONT Unable to add columns to tables on TOC pages
2880728 SYSTEM_CAPTURE UI System Capture hangs when user tries to select and move circuit or multiple wires
2908467 SYSTEM_CAPTURE UI topwb crash when using "make same size"
2850280 SYSTEM_CAPTURE UNIFIED_SEARC Scroll bar not coming or not scrolling till the end for classification filter
2879942 SYSTEM_CAPTURE UNIFIED_SEARC Unified Search Filter Panes
2884771 SYSTEM_CAPTURE UNIFIED_SEARC Unified Search Filter display issue
2839187 SYSTEM_CAPTURE VARIANT_MANAG VARIANT_DEVICE_TYPE is truncated resulting incorrect Variant BOM
2903062 SYSTEM_CAPTURE VARIANT_MANAG Syscap repeatedly crashes when trying to open a variant.
2908179 SYSTEM_CAPTURE VARIANT_MANAG Crash while updating the project
2908314 SYSTEM_CAPTURE VARIANT_MANAG System capture crashes while updating the design.
2827084 SYSTEM_CAPTURE VERSION_ON_SA Manual commit is prevented when symbol is missing in design cache but not autocommit
2886288 SYSTEM_CAPTURE VERSION_WIDGE System Capture exits on selecting a part in attached design
2768304 SYSTEM_DESIGN SDE_REPORTS Exporting Pin/Port B2B connector information as HTML or XLS file in SLD
2890237 SYS_RELIABILITY AUDIT_RULES Run Audit Schematic rules issue.
2890679 SYS_RELIABILITY AUDIT_RULES Running ERC takes too long on a customer design
2905747 TOPXP SYSTEMPI systempi simulation results will not be updated when using custom in simulation name option
2820871 TOPXP SYSTEMSI SystemSI cannot correctly give the result of the non-RX end of the channel after the repeater
2898487 TOPXP SYSTEMSI The stuck_low spice subckt does not get created when using spectre as the simulator in Topwb for a parallel bus analysis
2917629 TOPXP SYSTEMSI Can not change the poly value of PRBS stimulus pattern setting in SPB 23.1 HF1.
2899783 TOPXP TCL Cktnode match from file function does not work
OrCAD X is an innovative design platform that caters to the needs of individuals and small to midsize businesses. It focuses on providing a cohesive and comprehensive solution for all design requirements. The addition of the X in this new product platform signifies its ability to extend its capabilities to the Cloud, enabling users to leverage additional services like X AI.
OrCAD X Presto, a new layout environment within the OrCAD X platform, offers a cuttingedge solution for layout design. The interoperability between OrCAD X Presto and the existing PCB Editor ensures compatibility and easy transition of layout designs. OrCAD X Presto can be used in Cloud-connected and unconnected modes, allowing you to work flexibly based on your preferences and requirements.
OrCAD X Presto elevates the user experience by eliminating the need for modal dialog boxes. Instead, layout toolbars and floating menus are implemented, reducing distractions and ensuring the design space is always unblocked and accessible. This architecture significantly enhances productivity and allows designers to focus on their work.
OrCAD X Presto includes an integrated 3D viewer that seamlessly switches between 2D and 3D views. This feature enables designers to perform fast and accurate 3D analysis, supporting 3D clearance Design Rule Checks (DRCs). This integration enhances visualization capabilities, allowing the designers to identify and address potential manufacturing issues quickly and efficiently

OrCAD X







Learn about the OrCAD X Platform and see how it's capabilities and easy to use interface help you design fast, correct and connected.
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For.

Owner: Cadence
Product Name: OrCAD X Platform
Version: 2023 (23.10.002) Hotfix
Supported Architectures: x64
Website Home Page : www.cadence.com
Languages Supported: english
System Requirements: Windows *
Software Prerequisites: pre-installed OrCAD X Platform 2023 (23.10.000) and above
Size: 2.8 Gb



* System Requirements:

这是什么神级软件？

谢谢楼主分享。

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谢谢楼主，我看看是不是这个版本